fpga implementation of turbo decoder using QPP interleaver for wireless communications

Lukket Opslået 5 år siden Betalt ved levering
Lukket Betalt ved levering

I need to implement the project using fully parallel interleaver and QPP interleaver in FPGA platform. the language used for coding is Verilog and it is synthesized in Xilinx.

C programmering Elektronik FPGA Microcontroller Verilog / VHDL

Projekt ID: #17738298

Om projektet

6 bud Remote projekt Aktiv 5 år siden

6 freelancere byder i gennemsnit ₹11217 timen for dette job

NienYi07

I am a hardware designer in Silicon Valley, California USA specializing in the developing hardware for security firewall ASICs and FPGAs. Projects that i have completed include hardware schedulers, parsers, packet insp Flere

₹12222 INR in 7 dage
(0 bedømmelser)
2.7
belenkovroman

Great experience in FPGAs. Work with communication and information transfer systems. Work with digital signal processing

₹12222 INR in 10 dage
(0 bedømmelser)
0.0
Akritim

hello Myself Akriti electronics and communication engineering Student at NIT Jalandhar with 6 month experience in VHDL and system designing. But i am comfortable with VHDL using xilinx not verilog.

₹1500 INR in 3 dage
(0 bedømmelser)
0.0