fpga implementation of turbo decoder using QPP interleaver for wireless communications
₹1500-12500 INR
Betalt ved levering
I need to implement the project using fully parallel interleaver and QPP interleaver in FPGA platform. the language used for coding is Verilog and it is synthesized in Xilinx.
Projekt ID: #17738298
Om projektet
6 freelancere byder i gennemsnit ₹11217 timen for dette job
Great experience in FPGAs. Work with communication and information transfer systems. Work with digital signal processing
hello Myself Akriti electronics and communication engineering Student at NIT Jalandhar with 6 month experience in VHDL and system designing. But i am comfortable with VHDL using xilinx not verilog.