Design of a Deep and Superscalar MIPS Processor Pipeline
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I'm looking for someone to design a deep and superscalar MIPS processor pipeline for my graduation project. The goal of this project is to design a deep and superscalar MIPS pipeline. The design will be tested and verified using appropriate hardware description language (HDL) platform. Students would investigate different design alternatives before picking their solution for implementation. Designing a deep and superscalar pipeline involves not only increasing the number of pipeline stages, known as superpipelining, but also increasing the number of instructions issued concurrently. Thus, the dual objective of increasing the number of instructions running simultaneously at each clock cycle as well as reducing the average number of clock cycles per instruction (CPI) to be effectively less than one can be possibly realized. Combining a deep and superscalar pipeline would entail design changes to different components of the processor datapath, such as the ALU as well as the forwarding and control units. Simulation shall be used to test the implemented design using test programs containing both data and control dependencies.
Projekt ID: #36709017