Verilog 64 bit adder

Lukket Opslået 6 år siden Betalt ved levering
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Need a 64 bit adder than can deal with signed numbers.

Verilog / VHDL

Projekt ID: #13962873

Om projektet

12 bud Remote projekt Aktiv 6 år siden

12 freelancere byder i gennemsnit $73 timen for dette job

ahmedmohamed85

Dear sir I have more than 9 years experience in digital design using Verilog please check my profile also please message me so that we can discuss Best regards

$70 USD in 0 dage
(389 bedømmelser)
7.8
ducdctoandh

Dear customer, I am really happy to help you out of this project. I would like to introduce that I am an freelancer with 100% JOB COMPLETED in VHDL/VERILOG. I am really suitable for job description: First: I a Flere

$70 USD på 1 dag
(83 bedømmelser)
6.4
raulbehl

Hello! I am an experienced Engineer and have been helping out many on this platform. It would be great if I could help you out. Thank you!

$77 USD in 3 dage
(71 bedømmelser)
5.9
uetian09ee506

I am an Electrical Engineer having specialization in Electronics and Control, teaching at Electrical Department FAST National University Pakistan. I am also persuing my MS degree in Electrical Engineering with speciali Flere

$70 USD in 3 dage
(32 bedømmelser)
5.1
kulwantsingh16

A proposal has not yet been provided

$70 USD in 2 dage
(15 bedømmelser)
4.2
punamsengupta

A proposal has not yet been provided

$70 USD in 5 dage
(13 bedømmelser)
3.8
noyfris

I have a long time experience with HDL programming including FPGAs, CPLDs.. This is a project that can be implemented fast.

$77 USD in 2 dage
(0 bedømmelser)
0.0
fotrosna

hello this is your slice of code: f0 : fa port map(s14(0),c14(0), '0',product(0),x(0)); f1 : fa port map(s14(1),c14(1),x(0),product(1),x(1)); f2 : fa port map(s14(2),c14(2),x(1),product(2),x(2)); f3 : fa port Flere

$70 USD på 1 dag
(0 bedømmelser)
0.0
mangaljithummar

Hi, I am professional VLSI engineer working in ASIC design. I am interested in this project. I can provide synthesizable code along with testbench and simulation waveforms.

$77 USD in 10 dage
(0 bedømmelser)
0.0
VyomParikh

A proposal has not yet been provided

$80 USD in 10 dage
(0 bedømmelser)
0.0
mmonemvlsi

I have more than 12 years of experience using Verilog, I did lots of arithmetic blocks before including signed adders, I will be happy to do this project for you

$70 USD in 10 dage
(1 bedømmelse)
0.0