UDP data filtering using Xilinx Zynq 7000 family Socs

Lukket Opslået 6 år siden Betalt ved levering
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UDP data filtering using Xilinx Zynq 7000 family Socs (10 Gb SFP+ port)

FPGA Verilog / VHDL

Projekt ID: #14600641

Om projektet

6 bud Remote projekt Aktiv 6 år siden

6 freelancere byder i gennemsnit $1204 timen for dette job

ducdctoandh

I am really happy to help you out of this project. I would like to introduce that I am an freelancer with 100% JOB COMPLETED in VHDL/VERILOG. Relevant Skills and Experience FPGA/VHDL/Verilog/Zynq Proposed Milestones Flere

$1500 USD in 20 dage
(89 bedømmelser)
6.9
punamsengupta

A proposal has not yet been provided

$750 USD in 25 dage
(13 bedømmelser)
3.8
kalshareef

I have been working with ZYNQ FPGA for a while and I have a good understanding of the UDP protocol so I am confident that I can get the job done. Looking forward working with you. Relevant Skills and Experience Have b Flere

$1222 USD in 20 dage
(0 bedømmelser)
0.0