The firmware will need to have base functions for interfacing the Bluetooth...firmware will need to have base functions for interfacing the Bluetooth radio and other communication (i.e. UART, SD Card, Ethernet, etc. ) and loading the memory. Using Xilinx, VIVADO software. and also PicoZed 7010 SOM + FMC Carrier V2 (xc7z010clg400-1) processing system
I am a cryptocurrency miner, and I would like to buy a larger number of FPGA cards to mine with, specifically the Xilinx VCU1525 FPGA Card. I need someone to Program the card to mine a number of specific algorithms. Preferably the dagger hashimoto, Neoscrypt, Equihash algorithms, I need a quote on how much this will cost.
We are seeking a consultant to migrate several Xilinx K7, K7 Ultra and/or V7 FPGA-based DSP Apps (developed using Vivado) to OpenCL so they can run on Intel, AMD/ATI, NVIDIA and mobile GPUs. Ideally, the OpenCL acceleration would fit into our existing Windows / LabVIEW framework so we could have compatibility with our current set of apps.
Design Pipeline processor for RISC based instruction set on Xilinx ISE verilog for Spartan 3E board. Instruction set is given and we need certain kind of output based on designed assembly code. Code should be loaded on Instruction memory and it's already done. we have only 2 days for that but processor is 8bit and instruction is 16bit
I am looking at an FPGA project using xilinx the project has very specific functions that i do not have the skills required to implement it myself sadly so i hope you can help with that. The project is for a crypto miner that can mine using the cryptonote algorithm Variant 1 i have chosen a model of FPGA as it has 100k logic gates and good memory
We are looking for freelancer to develop FPGA software alghorithm for Cryptonight V7 mining using Xilinx Virtex UltraScale+ FPGA VCU1525 card. Develop FPGA bitstream for mining Cryptonight v7 (CN7) algorithm on Xilinx Virtex UltraScale+ FPGA VCU1525 card + modify the miner software on PC to communicate with the FPGA. Miner software can communicate
i need to design 8 bit pipeline line processor in xilinx ISE. It should be in verilog. there is 3 type of instruction set.
- Development Environment Tool : Xilinx Vivado and SDK Latest version Device : Xilinx Zynq7045 HDL : Verilog HDL Required IP Module :HDMI_RX, HDMI_TX Using PG235 [log ind for at se URL] Using PG236 [log ind for at se URL]
...pictures. We need a Zynq developer to write FPGA code that will process the pictures. We're using the Zynq 7010 clg225: [log ind for at se URL] Specifically, we want streaming FPGA code that will: 1. Subtract the median-filtered image from the original image (i.e. output = image
Hi Chris, I saw a message stating you had experience creating a FPGA miner. I am trying to learn how to program FPGA and wanted to start w...crypto miner so I can try to pay off the hardware. I am willing to pay to get some assistance and pointers and any example projects you are willing to share. My hardware is Xilinx AVNET VCU-1525 development kit.
BId only if u can do only the second Part for $50 an...seeing it through a stereoscope lensIn perspective projection and the use of two center projection (off-axis projection) 2,Implement hardware system using vhdl language and xilinx 9.2i software And executed on spartan -3e linen The graphic is displayed on an external screen only the second Part
We are looking for one freelancer to develop FPGA software for Cryptonight mining using Xilinx Virtex UltraScale+ FPGA VCU1525 card. You will have to program an FPGA card that I will provide, to work for crypto mining. Is necessary also customize mining software that works under Windows to by able to works with the FPGA. Software must have to be
...output stages in a manner that each output is 120 degrees off-phase with each other as shown in the attached image. No other work is needed at this point. I will provide a Xilinx Spartan III demo board made by Digilent ([log ind for at se URL]), if necessary and have it shipped to the developer. The developer
Hi, there I am looking for an experienced FPGA developer that can implement HASH algorithm on FPGA. We can discuss in details via chatting. Please contact me! I am waiting for someone now. Welp,
- PCI transmition logic implement with ZC102 board and Xilinx PCI Solution v1.3 - windows device - sample wndows program
Hi, This project is for a team of VHDL expert and Java expert. I have a dev. FPGA board embedded the chip AD9764. This is the DAC. It embeds the chip ADS5522 too. This is the ADC. I already have a not-completed project written in vhdl including modules parts of this project. I need you to simulate and fix the data transmission part between the client
Hi, This project is for a team of VHDL expert and Java expert. I have a dev. FPGA board embedded the chip AD9764. This is the DAC. I already have a complete project written in vhdl including other modules apart of this project. I need you to simulate and fix the data transmission part between the client application to the DAC AD9764, which is
...denke so im rahmen von 20-40h im mai. ich benoetige einen DMA test, also die maximale transfergeschwindigkeit von einem PDM pin (input) bis in den linux userspace. HW und xilinx build-server sind vorhanden. ich habe das board (z-turn myr) bis jetzt noch nicht getestet. das input sollte als vivado AXI4lite IP auf der GP clock (100MHz) rund um die 400
I am having difficulties in finishing my final year project. I would like to do Verilog codes on Fast Fourier Transform processor for both Radix-2 and Radix-4 of 8-bit by using Xilinx software. I need to get the test values design along with its output waveforms. I am working on a project of 'Design and Simulation of a Fast Fourier Transform Processor
I need someone to help me modify a Demo(FPGA: Xilinx Basys3 Language:Verilog) which is a object tracking system based on a pan-tilt. I think the modification won't be a big task, because the imaging processing algorithm works well, the need of modification is in controling two servos, especilly in getting back servos' position. The original demo
I am currently working on peak detector using VHDL entry (Modelsim and Xilinx), to design logic design in FPGAs to fulfill my free time. There are two parts, which are command processor and data processor. However, I have completed the data processor part, so only command processor left and I have no idea how to complete it. I plan to accomplish this
我公司有一个项目， cy7c68013A_128 单片机的软件开发， 细节是用GPIO模仿Jtag烧录两片Xilinx的PROM. (XCF04S, XCF01S). Xilin有比较详细的方案。 见副件。 如果你们承接这类工程， 请你给我一个报价。 我们有硬件平台， 你们需要提供， 1 windows usb 的驱动， 指定等待下载的文件。 Cy7c68013A 的程序，把指定的文件烧录到目标PROM. 启动系统， 读取FPGA内部寄存器，确定烧录成功。
Need a freelancer to port an old Altera(maybe even Xilinx ISE) project into Xilinx Vivado and provide the bitstream to run on a Digilint Zybo Zynq-7010. May be done very quickly since many files are already in a ISE project. Resources: [log ind for at se URL] [log ind for at se URL]
write vhdl code for : 1. (8 16bit register) register file/ a gate-level vhdl models for functional unit. + test benches and simulations. 2. implement a microprogrammed instruction set processor extended on part 1. more details to be given in chat. deadline 28/03/2018
Using a FreeRTOS and lwIP (TCP/IP) on Xilinx ZynQ SoC. Tool is Vivado 16.2 (SDK). At Ethernet interface (PS of ZynQ FPGA), mixed traffic is to be differentiated based on pre-defined IP and Ports and IP packets are to be routed to respective application. Rest all traffic (RAW Ethernet Frames) to be passed on to PL part (FPGA). This can be done by
• Target DDR3 controllers development for Frame buffer (on...for Frame buffer (one frame delay) • Features Frame Buffer input: 1920 x 1080@60 fps, YUV 4:2:2 output: 1920 x 1080@60fps, YUV 4:2:2 • HW Platform DDR3 controller for Xilinx Zynq-7000 or 7-series FPGA • Design output Verilog DDR3 controller source codes, testbench and document
We need to develop a QPSK demodulator FPGA xilinx based.
write an AI Algorithm for video codec h.264 and design Chip, after design chip of AI Based video codec h.264 you can verify out put on Xilinx FPGA Kit for face recognition in cloud iam expecting this project to finish on or before 26th feb2018 regards D RAMANNA [Removed by Freelancer.com Admin for offsiting - please see Section 13 of our Terms
AIM: DESIGN A CHIP FOR AI BASED VIDEO CODEC H.264 FOR FACE RECOGNITION IN CLOUD AND INTEGRATE WITH XILINX FPGA BOARD TEST OUTPUT. IAM EXPECTING TOTAL TIME PERIOD IS 6DAYS(25/02/2018) REGARDS D RAMANNA BANGALORE-INDIA [Removed by Freelancer.com admin]
AI Based Chip design for video codec h.264 on custom FPGA boards for face recognition in cloud expecting AI algorithm, os ,execution, chip design and testing on FPGA board Regards D Ramanna *Removed by Admin*
Chip design for AI based video codec h.264 with custom FPGA on Xilinx packages which is face recognition in cloud also. Iam expecting coding, execution, chip design&testing on custom FPGA board [Removed by Freelancer.com Admin]
Chip design of custom FPGA with xilinx packages for AI based video codec h.264 for face recognition in cloud
We are looking for develop and implement OFDM / 16QAM, 32QAM, 64QAM , 256QAM Modulation / Demodulation algorithm with Matlab and implement it on Xilinx Zynq FPGA . 1- BW : tunable upto 40Mhz . 2- FEC : LDPC or Reed solomon .
...[log ind for at se URL] Layout: [log ind for at se URL] Hardware: Zynq 7010 clg225: [log ind for at se URL] Python 1300 monochrome imager: [log ind for at se URL]
i have ADS5263 EVM board, and i connected that board with xilinx zc702 via ADC FMC adapter. i tried to write code for that i failed to generate bit stream based on xilinx application note xapp524. i need help to sort out the problem of clock multi region routing.
...programming, verification and validation. Proven experience in delivering at least one complex FPGA design project VHDL, Verilog based RTL design and development VHDL, Verilog based verification and validation Familiarity with Xilinx ISE, Vivado Design Suite Should have worked on ARM SoC based FPGA projects High Speed Data Acquisition
...and multiplying 2 floating point number values as follows: (2.32 + 3.65; 2.32 - 3.65; 2.32/3.65 ; 2.32*3.65) Must be done using a Matlab Toolbox for Xilinx . This code should work on Xilinx Spartan 6. Code must be simple and understandable with comments for each line of code. A page of Word document explaining the code with screen shots