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    Verilog project FSM Udløbet left

    Verilog project FSM Verilog project FSM Verilog project FSM

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    One of the most prestigious companies in the field of ASIC Design is looking for a talented Digital ASIC Designer. Previous work with SOC & Synopsys Design Compiler is an asset. The currently defined project is designing a miner chip (ASIC miner) based on the SHA-256 algorithm with the aim of reducing power consumption and improving speed. Send me a message if interested. Looking forward to your resume

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    I have launched a crypto Mining company and would like building a business plan along with financials & multiple stages. GPU & ASIC Mining Facility with a website selling capacity. i am looking for an experienced Crypto Mining business plan writer who understands the BTC Network and halving. and how to price model out finances on BTC Miners along with other miners & GPU based farms Ideally someone who can Scope and fixed fee per section but it's going to be ongoing work and updates needed as markets change

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    5G RAN FPGA Design Udløbet left

    ...have an internal project for 5G RAN FPGA design for DFE products: Skills: Job Description- Senior MTS RTL design 5G Product( 2 positions) · Candidate must have at least Bachelors or Masters EE - FPGA design experience (RTL Coding, comms, DFE(DPD, DUC, DDC, FFT, FIR, CFR) · Candidate must have verifiable experience for a minimum 6 years as a Verilog/System Verilog/ VHDL/RTL programmer with extensive Verification test bench development experience · Preferred prior project experience in 5G ORAN - RU/DU. DSP knowledge Matlab modeling is preferred. · eCPRI experience preferred . Special consideration will be given to those who have experience as 100G Ethernet or 10G Ethernet , IEEE 1588 · Knowledge of Queuing theory &mid...

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    I want you to desgin an IC chip description document. I need you to understand the verilog design and create some design descriotions, describing its fucntions in detail. The chip design has 3 main blocks ADC, PMU and sensors. These 3 blocks contain the most important functions of this chip. Please bid if you are experienced in wrting technical design documents for chip desing in detail. Thanks!

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    A presença de erros em dados digitais é um problema frequente em sistemas computacionais que lidam com transmissão e armazenamento de informação. Em alguns contextos, como o de computação aproximada, admite-se uma taxa ainda maior de erros para alcançar uma redução no consumo de energia. Nesses casos, torna-se imprescindível o controle de erros. Isto pode ser feito através do uso d...através do uso de códigos detectores (e corretores) de erros, que são capazes de detectar (e corrigir) a informação corrompida através de redundância inserida nos dados. Nesse projeto, o objetivo é gerar um codificador baseado em paridade e um detector de erros que avisa qu...

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    FPGA Packets Delay Udløbet left

    The project consists in implementing a buffer delay on a 100G traffic done in an Xilinx Alveo FPGA

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    I need to design a Hilbert transform and test it in Matlab before implementing it on FPGA. I have never created a Hilbert transform with Matlab without the hilbert() function, and the function does not return coefficients. I can't find the documentation on how to do it. I need someone to help with it. The Matlab code must also use the filter on sample data and return complex values after the transform. You should provide the Matlab code used to create the filter and get the coefficients. I will pay $70 USD for the task.

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    Hi Ahmed M., I noticed your profile and would like to offer you my project. We can discuss any details over chat.

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    The goal of the project is to design both hardware (PCB) and software for a low cost,small sized, digital video transmit...The interested designer can choose any processor or RF IC as per their wish but QFN/QFPN based IC will be preferable as they are easier to the image sensors/camera module should also be integrated into the AIO flight Controller can be based on Allwinner T113-S3 microprocessor or an FPGA but should contain Gyroscope, accelerometer, pressure/ project report will be sent to the intrested designers on request. An AI SoM board based on Rockchip/FPGA will also has to be developed under the design. The prototyping task will be undertaken by ourselves only the design of the video transmitter and the flight Controller needs to be done.

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    Hello, I need a Lattice FPGA specialist to review my simple LCMX02 Lattice PLD design. I can not make it work, and some help is needed to understand why the PLD does not respond to the JTAG file. This is a very specific project, specifically for Lattice FPGA. I designed with other types of FPGA, and got stuck when I switched to Lattice family of parts. Thank you!

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    I have the code for I2C slave. I want help in writing the verilog code for I2C Master testbench to communicate with the given slave. It can send a few i2C write and read commands (with address, data, etc). I have attached the code for I2C slave alonside for your reference.

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    code for SPI master to send data to a GPU. project setup for the customer's terasic FPGA board. assignment. demonstration of contents via zoom meeting. I will try to complete the project before the specified end date.

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    Hi Islam Muhammad S., I noticed your profile and would like to offer you my project. We can discuss any details over chat.

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    Hi Islam Muhammad S., I noticed your profile and would like to offer you my project. We can discuss any details over chat.

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    Simulation Udløbet left

    Vlsi project implementation of IIR FILTER

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    Creating 2-chain Arbiter PUF on specific FPGA with 64-stages MUX for each chain. The output response PUF will be sent to external device, i.e. Arduino (microcontroller). On the other words, the output response PUF will be processed further on Arduino/microcontroller device

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    Your job is to write verilog code for i2c communication and interface it with a processor. Take data from the slave through the accelerator and store it in a memory. Make the processor read the data from that memory and give its response. Now write that response data back to the slave.

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    SOC Verification Udløbet left

    Experience: 6-7 years Job Description: 1. Experience in ASIC verification, preferably baseband/ controller side 2. Experience in Industry standard protocols ARM Interconnects(AHB, APB), SPI, UART, I2C, DMA, Serial Flash, Security and Encryption. 3. Full chip SoC (C and SV based), Subsystem and Block/IP level verification. Test Bench generation with ability to run embedded C programs. Must have experience of 2-3 SoC verification. 4. Experience in HDL(Verilog, VHDL) and HVL(System Verilog, Specman) based functional verification. Experience in code coverage. 5. Experience in Verification methodologies(UVM, OVM and eRM). language simulation (Verilog-AMS, SystemVerilog). 7. Experience in Mentor, Cadence and Synopsys simulators. 8. Build automated Test bench and reg...

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    We are a Registered Training Organisation (RTO) We have one Dual Diploma on scope We have been trading since January 2022 (very recent) and our first intake of students was in March 2022. We only managed to get 6 students enrolled! This ...services. Is it possible you can give us a quote on this first year Audit please taking into consideration that we had only 6 students starting Mch 2022. The Audit of the financials requires Signed Auditors Independence Declaration Independent Auditor's Report A Copy of the Certificate of Public Practice certificate of the person conducting the audit Details of the auditors registration with ASIC NOTE: once i submit our application to the government it can take 10 months to be approved (or longer) hence there is an urgency to this audi...

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    I need Verilog code for Energy-Efficient Logarithmic Square Rooter. It should be done within 1-2 days maximum.

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    ASIC designer Udløbet left

    One of the most prestigious companies in the field of ASIC Design is looking for a talented Digital ASIC Designer. Previous work with SOC & Synopsys Design Compiler is an asset. The currently defined project is designing a miner chip (ASIC miner) based on the SHA-256 algorithm with the aim of reducing power consumption and improving speed. Send me a message if interested. Looking forward to your resume

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    It is required to generate arbitrary signals in FPGA for Real Time Controls using Servo Proportional Valve with Control signals of ( +/- 10 VDC ). The various types of other signal generation in FPGA besides Arbitrary signal can be Square, Sine, Triangular. Generation of white noise signal for Real time control is also required.

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    Need help with code and set up for SPI protocol to send data from an FPGA to a GPU, explain code/software procedure and wiring. can forward technical specs for both devices to be used

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    I am looking to develop a Verification Code using System Verilog for USB 2.0 Protocol and also I want a verification plan for that . Kindly note that I want Complete TB code for all the components in Environment and also Test and Top instances as well . For any query/ or clarity ping me.

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    Hi Islam Muhammad S., I noticed your profile and would like to offer you my project.

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    A complete color sorter Machine Firmware needs to be converted into Intel Quartus Project, The project contains IP Cores as well as softcore processor and the verilog coding part, All these to be integrated as a single bit file and to be implemented it on a Cyclone V FPGA Board.

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    Hi. Attached a few spike from scope capture. Need at least 8 channels simultaniously. 1. how to get detect these with a precision of 1mV? 2. how to get the value in stm32? (worked with these a lot) (or do we need an fpga) Freq is 200hz at first. Looking to get to 1 khz in the near future. Duration of the spike is only 5 to 12 microseconds. What is the best way to do this precisely ? heard tons of ideas (peak-detect circuit, 20 msps adc, etc ) , but need real proven experience. !!! please apply only if done this succefully. In the opening bid propose direclty your solution. Biggest bids will be disqualified. Stop bidding the top of freelancers brackets. No B*****S approach. Will be paid only if it WORKS! Need STM32 code, parts id, and pcb design.

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    I have attached the details below

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    Vlsi engineer Udløbet left

    I have attached the details , i want to complete a project

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    LabView- Code for FPGA to read temperatures from MLX90614 Sensor using I2C Protocol and Compact-RIO Hardware.

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    FPGA Programmer 1 Udløbet left

    The project requires an Embedded Programmer having experience in Driver Programming for FPGA cards, PCIe Interface and YOCTO as well as upbringing the Linux OS. Please DO NOT APPLY, if you DO NOT HAVE THE REQUIRED EXPERIENCE.

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    Need a stand alone BMS program that monitors temperature and flow rate for a minimum of 3 liquid loops: ASIC coolant loop, Domestic Hot Water, & Industrial Hot Water. BMS needs to communicate with BRAIINS OS software to manage ASIC operation to prevent ASIC overheating. BMS needs to be able to be controlled and monitored remotely.

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    Trophy icon I need a new business Name Udløbet left

    My business is a preloved luxury store. We sell second hand clothing, handbags, footwear and accessories. I need a NEW business name that is catchy and easy to remember. Something that would resonate with the feeling of luxury and sustainable fashion at the same time. My current business name that needs changing is Mrs Kitnar. My current website is and my Inst...same time. My current business name that needs changing is Mrs Kitnar. My current website is and my Instagram page is Mrskitnar. Please feel free to have a look and see what it is all about. I have attached my current branding. Please note that the business name must be available to use in Australia in order for the contest winner to be successful. (This can be checked on the ASIC website) Thankyou

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    Survey paper writer Udløbet left

    I need a survey paper based on 3 articles at your choose from with publication date more recent then 2010. The articles has to be based on one topic from the following. Theme variants: A. Digital signal processor architectures (e.g .: DSP, ...recent then 2010. The articles has to be based on one topic from the following. Theme variants: A. Digital signal processor architectures (e.g .: DSP, VLIW, etc.) B. Micro-architectures optimized for digital signal processing (e.g., multi-port memory, SIMD register banks, multi-core, multi-threading, etc.) C. Accelerators for digital signal processing (rapid deployments / energy efficient with FPGA, GPU, etc.) The paper must be written in latex format. 4 pages, 3-4 figures (explained) and also some references from other articles.

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    Implement the circuit design in the FPGA, and read input /write output to the file. Including timing analysis, power consumption and pin planner etc... Using Quartus prime

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    FPGA Project Udløbet left

    I need to do simple FPGA project on Boolean Board (Real Digital). For example Tic Tac Toe game. software should be Vivado and programming should be done in Verilog.

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    Explain and help understand Ethernet MAC/PHY RTL from github. Required: - Industry experience in digital/mixed-analog IP RTL design, preferably Ethernet IP. Meetings will be conducted via zoom/meets. Thank you!

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    Program on vivado (verilog), morse code. Binary for "BASYS 3" fpga, simulation, files...etc More details via chat

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    ...sent) and get quotes from them. I will provide an email you can use to email each vendor. I have also provided a link to the item. They can’t be any random emails. I need screenshots of the company’s website and the contact information for each company. Item: FPGA STRATIX 10 2912FBGA (1SX250HH2F55E2VG) Part Link: Hello, my name is Edwin Mendez. I am writing this email on behalf of my company. We are looking for a particular part. The part that we are searching for is the FPGA STRATIX 10 2912FBGA (1SX250HH2F55E2VG). We need three of these parts ASAP. It would be great if you can provide us with this particular part. We are ready for any deal regarding the price structure. We can also schedule a meeting for any further discussions.

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    I need to implement an Ed25519 Algorithm in Verilog for FPGA implementation that can properly simulate on Xilinx Vivado Design Suite. The complete algorithm code is already available in C language and I want to convert it into Verilog. Link:

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    Given any Verilog netlist of a digital circuit in gate-level format, the code should extract critical path. Critical path is the longest path from input to output port. There could be multiple inputs/outputs in a given circuits. Critical path can be the longest path from any input to any output based on the connections in the circuit.

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    need to make truth table and Circuitry Design and verilog code and testbench for fibonacci series generator

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    FPGA Developer Udløbet left

    I have rich experience with FPGA I developed FPGA based IDS(Intrusion Detection System) I am strong at C, C++, Verilog and son on

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    using Artix 7 implement Master UFS protocol design for the UFS Host device, Feel free to contact who's have experince on Stroage's(emmc, ufs, nand e.t.c) Skills required : Verilog , VHDL , C , C++

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    We hire freelancers who have 1 to 3 hours of free time per day and need a better iPhone 7 or above that can perform and complete testing tasks well. Test system design. Areas of expertise include embedded system/FPGA development, hardware prototype stability and testing. We make the world a better place through innovation and collaboration. From the bottom of the ocean to outer space, you can contribute to the important work of a company whose values are made up of diversity, fairness and inclusion. We are committed to creating a warm, respectful and inclusive environment for all of our teammates and providing them with good career development opportunities. Find the future with us.

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    I am looking for embedded developer to help me on preparing linux image for FPGA and SOC chip . Have samples and you need to follow and prepare the image

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    I am looking for an electrical engineer who can work on FPGA TEST Board design. The project is to design FPGA TEST Board for XC7VX690T-2FFG1157I chip. We need power supply connectors as Banana jack and JTAG, UART, and SPI flash, and other decoupling capacitors and resistors. We just need simple workable Sch and PCB design wit optimal design. The candidate should have rich experience in FPGA PCB design using Altium.

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    Assalam o alaikum !!! We are looking for electrical engineers to join our team and work on different projects related to following domains of electrical engineering: 1) Control System 2) Satellite communication 3) Radio frequency and microwave circuit design 4) VLSI techniques 5) Radar theory and satellite communication 6) Intelligent and adaptive systems 7) Digital design 8) Asic design Freelancers must be proficient in following: 1) Matlab / Simulink 2) Proteus 3) Multisim 4) pspice 5) LTspice 6) VHDL/Verilog coding What I am expecting: 1. Dedication to the work 2. On time delivery of work without any delay 3. Well arranged and properly formatted reports with plagiarism count below 10%

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