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    2,238 vhdl vga virtex2 jobs fundet, i prisklassen EUR

    Need to update VHDL and C-Code for change the communication from PCI-e to USB. The target is a Xilinx FPGA

    €498 (Avg Bid)
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    3 bud

    The project is described in the uploaded file, however one can alter the project as long as keeping the equipments and the goal of the project intact

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    4 bud

    Hello i have a code of piano synthesizer using VHDL (vivado) and i want to understand it and fix it ... can you help me ?

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    1 bud

    ...ability to extract and critically evaluate data for an unfamiliar digital design problem.‎ • The application of appropriate design methods to the VHDL design.‎ • The selection appropriate analysis tools, VHDL model abstraction levels and simulation test vectors.‎ • Ability to implement your design solution on a commercially available digital Computer

    €49 (Avg Bid)
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    7 bud

    I need someone to write verilog code and also test .do files for a maze game. The program should output to vga. The rules of the game are simple. You start at a point and have to figure out how to get to the exit just like an actual maze. However, there is a monster chasing you and if he catches you, you are dead. The player's movement should not be

    €154 (Avg Bid)
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    4 bud

    ...code and also test .do files for a simplified board game. The program should output to vga. the game is quite simple ;2 players roll dice and move x amount of squares according to the number rolled. first to the end of the board wins. We can discuss the details. The vga display should be very simple and custom made -- not imported from a library etc.

    €137 (Avg Bid)
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    2 bud

    ...already have this you can modify that but I need the code running on FPGA board after I download it to it. Description: You have to create the VHDL model for the 4-bit multiplier. You must also synthesize the VHDL model, download to FPGA and test your multiplier on the FPGA board. Use a push button on the DE10-Lite FPGA to provide the clk input to the

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    You have to build an address block using VHDL

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    hello, I have this project where I need to read from files and print the output in one file. I provided a very similar code , that can be modify and Matlab code to generate input files.

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    To stimulate a project-based evaluation approach using VHDL and write a report. More information is contained in the file. Projects need to be written in VHDL and run a simulation for the program using a board. I will need the VHDL code and simulation for the timing diagram.

    €35 (Avg Bid)
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    AXI FULL FIFO debug Udløbet left

    I created this project and fini...created this project and finished the entire code ,but for some reason it is not giving me the correct outputs.I would like help to fix the issue by editing my code. using VHDL in vivado I was able to create successful circular cordic. but when I made my AXI full and run it in SDK, it did not give me the right answer

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    A task compromising of Counter, clock divider, clock enable (CE), and seven-segment display using VHDL and Xinlinx Vivado. Further details will be provided. Deadline 3 days.

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    I'm building a subscription website and want to upload (I currently copy and paste) csv spreadsheets to Google Sheets. The spreadsheets currently are created by vba scripts...and want to upload (I currently copy and paste) csv spreadsheets to Google Sheets. The spreadsheets currently are created by vba scripts and I prefer to keep everything in vga.

    €141 (Avg Bid)
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    10 bud

    ...ability to extract and critically evaluate data for an unfamiliar digital design problem.  The application of appropriate design methods to the VHDL design.  The selection appropriate analysis tools, VHDL model abstraction levels and simulation test vectors.  Ability to implement your design solution on a commercially available digital Computer Aided

    €66 (Avg Bid)
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    5 bud

    ...attached the full site survey plan for a block of land with a fall in the block from rear to front of the block. I would like you to amend and place this building on the casa-vga-diseno-norteno in the title. You will need to retain a 1m side boundary and 9 m front boundary. The lower floor rooms will need you to draft the plans with the them cut into

    €133 (Avg Bid)
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    am a master student, studying embbeded microelectronic and wireless systems, i need a vhdl code for dual_4_1 multiplexer, for structure, behaviour and dataflow if possiblr. thank you

    €19 (Avg Bid)
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    The goal is to design a game on Xilinx FPGA. More details on chat. The deadline will be 3 days. Only serious bidders who can complete in 3 days should bid. No Excuses. Time wasters avoid bidding, please.

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    This is a vhdl and C++ project. requires knowledge of both VHDL and C++

    €18 / hr (Avg Bid)
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    Expert on VHDL needed to integrate custome VHDL system in Vivado. He is also expected to create a custome SDK app that can handle this custom peripheral. Please bid if you can do. Due in 36 hours

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    3 bud
    VHDL expert needed Udløbet left

    Expert on VHDL needed to integrate custome VHDL system in Vivado. He is also expected to create a custome SDK app that can handle this custom peripheral. Please bid if you can do

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    Project for Loi L. Udløbet left

    ...board : DE10-Lite MAX10 10M50DAF484C7G - monitor : HP Compaq LA2205wg, VGA mode 1680x1050-60Hz - OS : Linux distro (Linux Mint). - language : VHDL - IDE : Quartus Prime Lite Edition - Simulations with ModelSim - mini-project : 0) implement a 1680x1050-60Hz mode VGA controller (operating @ 143Hz pixel clock via PLL) 1) store 280x280 8byte/pixel

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    i have attached the document below. And i need this on 21st of october.

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    ...have to be ported to VHDL and be integrated before programming the Xilinx V6 FPGA on the transmitter. Complete hardware and many of the software blocks in VHDL are already built by our team. The requirement is urgent. Entire work to be completed in 2 - 3 weeks. Any freelancer with experience in integrating system level codes in VHDL, basics of digital

    €766 (Avg Bid)
    Lokal
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    Need an expert in xilinx vivado Projects are based on digital systems on topics such as Multiplexers Flip flops registers Counters Clock dividers Please contact for project instructions and further details

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    Snake Game : 1.) Should run on Altera DE2 Board or on basy3 . 2.) Should Support VGA. 3.)Needed in a 3 days. skills:- verilog software:vivado i need this project in verilog and not in VHDL

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    I would like to discuss with freelancers having strong expertise in programming languages like VHDL, Verilog, Matlab, embedded C Please reach out to me. Engineering B.Tech. is must

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    30 bud

    Any encryption code (AES/RSA) written in VHDL/Verilog in Quartus II for fpga board stratix IV. Please contact for more details.

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    risc processor design and test, more detail I will provide on chat

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    Create a custom SPI master controller with single, dual, and QUAD operation modes in VHDL for a MAX V CPLD.

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    This is pavan. I am from the VLSI industry. I need a technical writer to explain 3 subjects(digital electronics, Verilog, and VHDL).

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    Necesito una persona que cumpla los siguientes requisitos: - Portátil con entrada de red/ethernet y salida VGA ó HDMI. - Nociones básicas de conexiones audiovisuales. ( VGA, HDMI, mini-jack, jack, etc...) - Ser autonomo El trabajo consiste en conectar un portátil a un proyector en un hotel de la ciudad de Santander y proyectar un vídeo. El evento

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    Lokal
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    Need to set up a Cisco SX80 system / Clear choice sound system / VGA / HDMI / VCR / DVD and 2 cameras all programmed on two tablets.

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    Lokal
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    The aim of the project is to design a BIST controller to insert and detect the faults (defect) like Read ...disturbance, Erase disturbance, Program disturbance, SAF, TF, ADF, CFs, TF, NPSF, Retention fault in FLASH memory by using BIST algorithm like March algorithm using verilog or VHDL in Xilinx or Modelsim. Need Simulation waveforms for the same.

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    Vhdl LCD finctional Udløbet left

    In ready projekt on vhdl (tic tac toe game) I need to add state od the gamę on LCD [log ind for at se URL]

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    I need to write a VHDL code for transfer data from 2 zedboard using ethernet without using a zynq-processor

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    I have a short project to do for an Altera 5M160Z CPLD (160 LE). This board has a 16-bit bus from a MCU and 8 control lines and output to a 10-pin port. What I need is a VHDL project (Quartus) that will implement a custom full duplex parallel to serial design. Development using simulation is fine.

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    10 bud

    add memory protection into the operating system, This project needs both hardware and software knowledge, you will be creating / implementing OS functions on the PicoBla...hardware and software knowledge, you will be creating / implementing OS functions on the PicoBlaze, programming in assembler. You may also need to modify the hardware using VHDL.

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    Hello guys I will need these simple tasks for $10USD the deadline is today 8 September. Description In C language, i will need embedded a median filter that I need to pass after a FPGA microblaze with image data (128x128) (with and without cache memory). I would like comments on the code and the new resulting image as deliverables. I attach the image table in the files section. Thank you a lot...

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    Hello guys I...cache memory). I would comments on the code and the resulting image as deliverables. 2) I need just a divider in vhdl language to pass through and confirm with numbers that it works. Again comments on the code please. P.S.: 8 by 8 vhdl integer divider I attach the image table in the files section. Thank you a lot for your bidding :)

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    écrire un code vhdl , pour DE0 nano , permettant de lire la température a partir d'une entrée analogique avec un LM19 et en sortie il faut emmètre des son avec un buzzer ( différent fréquence en fonction de la température )

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    Hello guys I will ...language, i will need embedded a median filter that I need to pass after a FPGA microblaze with image data (128x128) (with and without cache memory) 2) I need just a divider in vhdl language to pass through and confirm with numbers that it works I attach the image table in the files section. Thank you a lot for your bidding :)

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    I need help with the structural in Xilinx. I will give you full details. Regards

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    ...looking for Electrical & Electronics engineer Mechanical Engineer Civil Engineer Engineers should be expert in following fields Arduino Matlab Raspberry Pi FPGA Verilog/VHDL Python PCB Design (Eagle/Altium) Solidworks AutoCAD if you are expert in any of above mentioned fields then you can place a bid. We will prefer fresh Freelancers but having

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    Hi, my name is Paride, nice to meet you. i have got your conctact from Alessandro, a classmate. I am working on a easy Vhdl project, i already wrote all the code, the simolulation is working, but i need your help for two fast tasks: • I need to assign the pins on my FPGA, i can't find the correct pin of 2 serial signals. • i need you to check if the

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    Implement an AD2949 IC input block and some more

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    I want a content writer who knows digital design or digital electronics and vhdl subjects very well.

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    PRESENT-80 Udløbet left

    Hi there! I'm based in Ahmedabad, India. This project is related to lightweight cipher, cryptography. I have attached a pdf containing information relevant to this project w...design so that I can perform power analysis on it. Need the code properly working in two days. I looking for a Clock based implementation on existing design Language used : VHDL

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    Hi there! I'm based in Hyderabad, India. This project is related to cryptography. I have attached a pdf containing information relevant to this project which can be found...clock based design so that I can perform power analysis on it. Need the code properly working in two days. Note: Clock based implementation on existing design Language used : VHDL

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    ...uuid=f5dbdd1e-d9fa-4b3d-b98a-2870d47fd3d2' -smp '8,sockets=2,cores=4,maxcpus=8' -nodefaults -boot 'menu=on,strict=on,reboot-timeout=1000,splash=/usr/share/qemu-server/[log ind for at se URL]' -vga std -vnc unix:/var/run/qemu-server/[log ind for at se URL],x509,password -cpu kvm64,+lahf_lm,+sep,+kvm_pv_unhalt,+kvm_pv_eoi,enforce -m 16512 -vnc 0.0.0.0:100 -device &...

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    Науково-дослідний проект в галузі неруйнівного контролю. ____________________________________________________________ Scientific research project in the field of non-destructive testing.

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