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    2,195 vhdl vga virtex2 jobs fundet, i prisklassen EUR
    PRESENT-80 5 dage left

    Hi there! I'm based in Ahmedabad, India. This project is related to lightweight cipher, cryptography. I have attached a pdf containing information relevant to this project w...design so that I can perform power analysis on it. Need the code properly working in two days. I looking for a Clock based implementation on existing design Language used : VHDL

    €48 (Avg Bid)
    €48 Gns Bud
    6 bud

    Hi there! I'm based in Hyderabad, India. This project is related to cryptography. I have attached a pdf containing information relevant to this project which can be found...clock based design so that I can perform power analysis on it. Need the code properly working in two days. Note: Clock based implementation on existing design Language used : VHDL

    €26 (Avg Bid)
    €26 Gns Bud
    2 bud

    ...uuid=f5dbdd1e-d9fa-4b3d-b98a-2870d47fd3d2' -smp '8,sockets=2,cores=4,maxcpus=8' -nodefaults -boot 'menu=on,strict=on,reboot-timeout=1000,splash=/usr/share/qemu-server/[log ind for at se URL]' -vga std -vnc unix:/var/run/qemu-server/[log ind for at se URL],x509,password -cpu kvm64,+lahf_lm,+sep,+kvm_pv_unhalt,+kvm_pv_eoi,enforce -m 16512 -vnc 0.0.0.0:100 -device &...

    €25 (Avg Bid)
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    4 bud

    Науково-дослідний проект в галузі неруйнівного контролю. ____________________________________________________________ Scientific research project in the field of non-destructive testing.

    €342 (Avg Bid)
    €342 Gns Bud
    3 bud

    Hi there! I'm based in Hyderabad, India. This project is related to cryptography. I have attached a pdf containing information relevant to this project which can be ...individual modules are successfully executing but the final result doesn't appear which you can help me in debugging the same ) Note: Problem in debugging the code Language used : VHDL

    €138 (Avg Bid)
    €138 Gns Bud
    9 bud
    need expert on VHDL Udløbet left

    expert on VHDL is need for a project on digital thermostat. This is a simple task. expert only should bid

    €66 (Avg Bid)
    €66 Gns Bud
    20 bud

    build a communication block in VHDL at Xilinx environment

    €352 (Avg Bid)
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    14 bud

    Implement Communication VHDL Comm port on Xilinx FPGA part

    €110 (Avg Bid)
    €110 Gns Bud
    16 bud

    i need explained how to do impedance matching when making transmission cables for cvbs/vga signals to tv/lcd/monitors pc

    €27 (Avg Bid)
    €27 Gns Bud
    7 bud
    Task in VHDL Udløbet left

    i have a task related to Communication VHDL Xilinx, i will share the details in chat.

    €101 (Avg Bid)
    €101 Gns Bud
    19 bud
    €166 Gns Bud
    13 bud
    i neeb vhdl project Udløbet left

    i need vhdl project for fpga bord i need skeleton and can move

    €21 (Avg Bid)
    €21 Gns Bud
    14 bud

    Need help developing a face detection system with the DE2-115 board and OV7670. I already developed the code for the face detection but in MatLab.

    €193 (Avg Bid)
    €193 Gns Bud
    14 bud

    i want to realize the transfer function on fpga so any one with knowledge of vhdl and quartus tool can bid Thank you

    €32 (Avg Bid)
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    6 bud
    vhdl project Udløbet left

    I need you to implement a vcdl design project

    €63 (Avg Bid)
    €63 Gns Bud
    16 bud

    Software Engineer with Experience in C++, Data login, A/D Converters, DAC , HMI, LAN data collection , hardware knowledge deisred enougj to gnerate schematic vga, rs232,, Microprocessor ARM, Raspberry Pi or Beagle black experience a plus.

    €1272 (Avg Bid)
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    13 bud

    ...in der Digital- / Analotechnik - Kenntnisse von Simulations- und Prüfumgebungen - Kenntnisse mit technischer Dokumentation/Nachweisführung. Technisch: - OrCAD, PSpice, FPGA/VHDL, C++ - DO-254, MIL-STD-1553...

    €5070 (Avg Bid)
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    3 bud
    Tic Tac Toe in VHDL Udløbet left

    I am looking someone who can fix the errors of the game tic tac toe in VHDL for DE2-115 and prepare report.

    €66 (Avg Bid)
    €66 Gns Bud
    4 bud

    I need you to develop some VHDL designs for me. I would like this software to be developed in VHDL hardware descriptive language. With a  VHDL design and simulation

    €220 (Avg Bid)
    €220 Gns Bud
    3 bud

    this is my brief description of my project and please only serious people who would like to work and help me make a bid MY FPGA board is DEO nano SOC CYCLONE 5 1. reading an anolog signal (adc is available on board )ltc2308 is the adc which is available on fpga a board 2. realization of PID controller on FPGA 3. realization of process module on fpga (simple equation as to be realized here i.e P...

    €320 (Avg Bid)
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    2 bud

    firstly i am posting this second time because the guy called https://www.freelancer.com/u/ahmedmohamed85?ref_project_id=17168255 (Ahmedmohamed85) has showed is arrogance and negligence after accepting my project and asked me to create a milestone and cancelled it and made me to wait for 3 days without answering please guys kindly dont get fooled with such experienced guys and ruin your money and t...

    €51 - €122 / hr
    €51 - €122 / hr
    0 bud
    €14 / hr Gns Bud
    12 bud
    VHDL coding Udløbet left

    HDL coding from block diagram and pseudo algorithm

    €22 (Avg Bid)
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    5 bud

    Develop a musical bell that will play a selected and programmed song in the FPGA.

    €75 (Avg Bid)
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    4 bud

    Hi, I have opencv python programs want to implement them on the ZYNQ SoC. To be in precise want to implement custom object detection(using opencv, tensorflow)...implement them on the ZYNQ SoC. To be in precise want to implement custom object detection(using opencv, tensorflow) on to ZYNQ board. And also converting the python program to VHDL/Verilog.

    €116 (Avg Bid)
    €116 Gns Bud
    7 bud
    VHDL expert needed Udløbet left

    Expert in VHDL needed to work on a code

    €11 / hr (Avg Bid)
    €11 / hr Gns Bud
    14 bud
    Code Conversion Udløbet left

    Small project to write in VHDL

    €97 (Avg Bid)
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    24 bud

    Implement an algorithm in vhdl done in Matlab using System Generator

    €85 (Avg Bid)
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    11 bud

    ...5ms / 20ns = 125000 dcycle_mid = (dcycle_max – dcycle_min) / 2 = 75000 Για την περιστροφή του servo θα χρησιμοποιήσουμε τα δύο κουμπιά π&omic...

    €35 (Avg Bid)
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    1 bud

    1. Create a top level VHDL file for the project. VHDL code should be well formatted and commented. 2. Add two instantiations of a sync counter to the top level that are customized for the horizontal and vertical sync signals 3. Adapt the tesbench from homework 2 to simulate the top level file. Simulations should be annotated to depict events important

    €67 (Avg Bid)
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    6 bud

    Necesito hacer un programa en VHDL de un reloj (formato 24hs), con cronometro y con alarma. Cuando cambio a cada uno. no se debe perder la cuenta de la hora, cronometro o la alarma seteada. El reloj, la alarma y el cronometro se debe poder cargar/modificar manualmente. Detención y reinicio del cronometro. Cuando la hora del alarma coincida con el clock

    €158 (Avg Bid)
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    1 bud
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    Need to Develop one VHDL Program. more details will be provided on chat.

    €18 (Avg Bid)
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    1 bud

    Implement a program on VHDL

    €26 (Avg Bid)
    €26 Gns Bud
    1 bud
    hardware Design Udløbet left

    vhdl code for wireless adhoc network and its implementation in FPGA,

    €123 (Avg Bid)
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    4 bud
    Motor Control Udløbet left

    Convert C code to VHDL for BDLC, see attached datasheet. C code is available from TI website (or I can provide). Need to convert code, which is based on document into VHDL. Deliverables: VHDL code + working testbench + block diagram Need to be knowledgeable in Motor Control, C/C++ and VHDL.

    €364 (Avg Bid)
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    15 bud

    having some obstacles on monitor by using vga driver and an object will slide which will try not to crash a few obstacles

    €31 (Avg Bid)
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    1 bud

    Help with a few questions on VHDL

    €23 / hr (Avg Bid)
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    14 bud

    The purpose of this lab is to design a VGA driver to display 256 different colors on a monitor. Two timing signals are generated in this system, vsync and hsync to synchronize the plotting of vertical and horizontal pixels, respectively. The color data of each pixel is generated using an 8 bit counter whose first 3-bits are for red, next 3-bits are

    €31 (Avg Bid)
    €31 Gns Bud
    7 bud

    I want someone to write in vhdl an 8-bit harvard architecture CPU

    €128 (Avg Bid)
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    4 bud

    BId only if u can do only the second...dropping it and seeing it through a stereoscope lensIn perspective projection and the use of two center projection (off-axis projection) 2,Implement hardware system using vhdl language and xilinx 9.2i software And executed on spartan -3e linen The graphic is displayed on an external screen only the second Part

    €155 (Avg Bid)
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    2 bud

    Write a VHDL code to use two ultrasonic sensors as detectors, placed one at entrance and other at exit of a parking space. When the ultrasonic detects a car, use a counter to count the cars entering and decrement when a car exits. There is an RGB led place at each gate (entry &exit) which is used to indicate opening and closing of gates. Entry gate

    €26 (Avg Bid)
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    2 bud

    working with a grideye infrared sensor and looking to send the data through a wifi Cypress connection. We have some experience with this already but i am looking ...this so that we can work back and forth to get this up and running. I would like to send the data to a be read out with a Visual C sharp interface. Experience with FPGA and VHDL is a bonus

    €1753 (Avg Bid)
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    12 bud

    I require source code for the design and simulation verification of a calculator (Not + - / * operations) with slightly more experienced VHDL'ers can be selected for this quick project

    €20 (Avg Bid)
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    16 bud

    I require a VHDL deisgn code, to construct a simple calculator for two input numbers, testbench and simulation for verification of functionality before using the board.

    €8 / hr (Avg Bid)
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    18 bud

    Design a 3-phase 500Hz FPGA based generator driving a quad-channel DAC (only 3 channels needed) such as the LTC 2624. The overall idea is that; following <RESET> a table of values representing a sine wave shall be stored internally and scan sequentially by the three output stages in a manner that each output is 120 degrees off-phase with each other as shown in the attached image. No othe...

    €95 (Avg Bid)
    €95 Gns Bud
    10 bud

    I need some help with VHDL/FPGAs. I am stuck with some part and would like to fix it asap.

    €107 (Avg Bid)
    €107 Gns Bud
    7 bud

    I have a Spartan 6 lx9 dev board. I would to connect the board to my computer and perform standard arithmetic calculations and will require help setting up the calculator.

    €38 / hr (Avg Bid)
    €38 / hr Gns Bud
    13 bud
    fpga soft radio Udløbet left

    Hi, This project is for a team of VHDL expert and Java expert. I have a dev. FPGA board embedded the chip AD9764. This is the DAC. It embeds the chip ADS5522 too. This is the ADC. I already have a not-completed project written in vhdl including modules parts of this project. I need you to simulate and fix the data transmission part between the client

    €334 (Avg Bid)
    €334 Gns Bud
    4 bud

    I'm currently a 4th year degree student undergoing a project to build a Multiplexed DDS using iCE40UP5K breakout board. Apart from the Multiplexed DDS core itself, an i2s module for a DAC chip, Encoder modules for control of waveform parameters and an LCD module are present. Functional verification is done and behavior in simulation is as expected. What is needed is proper post-synthesis ...

    €102 - €509
    Fremhævet Haster Forseglet
    €102 - €509
    4 bud