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    2,945 vhdl fpga jobs fundet, i prisklassen EUR

    Diseñar un procesador que configure el SPI con el módulo nrf24l01, y luego mandar mensajes en radio frecuencia entre dos módulos nrf24l01

    €466 (Avg Bid)
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    3 bud

    Diseñar un procesador que configure el SPI con el módulo nrf24l01, y luego mandar mensajes en radio frecuencia entre dos módulos nrf24l01

    €221 (Avg Bid)
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    2 bud

    We are looking for someone with engineering background, preferably knowledge in FPGA related stuff to translate some tehnical documents. Google translate is not acceptable.

    €47 (Avg Bid)
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    26 bud

    I need to write a VHDL code for transfer data from 2 zedboard using ethernet without using a zynq-processor

    €176 (Avg Bid)
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    11 bud

    Looking for a mentor in advanced FPGA development using Altera Max 10 FPGA board specifically.

    €16 / hr (Avg Bid)
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    9 bud

    1. Identify a good value and properly sized CPLD/FPGA and toolset (toolset needs to be relatively easy to configure) to accommodate the required functionality. 2. Develop the CPLD/FPGA code. The device needs to take as inputs a set of states (from a microcontroller so either as an I2C command or as a 3 digital input code, along with 3 digital inputs

    €106 (Avg Bid)
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    16 bud

    I need a network of thermostats that send data over Power Line Communication to a router where it is then sent over Ethernet and stored on a server. I will need to have software to access and display the data in graph form. There are other components that I need that are not so detailed. I need consulting for the design and components to use for both the thermostats and the modem/router as well a...

    €123 (Avg Bid)
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    7 bud
    PCB design 1 day left

    ...square or rectangular with maximum dimensions of 9.5 cm x 9.5 cm. The PCB should hold 5 of the following boards: [login to view URL] There should be some minimal interconnection between the 5 boards (more details to be provided). The USB ports on each of the boards will be used only for programming

    €335 (Avg Bid)
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    23 bud

    I am looking for Xilinx SDx OpenCL expert, who can convert github miner project into FPGA hex file in Xilinx SDx. Don't bid if you do not have experience.

    €4266 (Avg Bid)
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    8 bud

    I have a short project to do for an Altera 5M160Z CPLD (160 LE). This board has a 16-bit bus from a MCU and 8 control lines and output to a 10-pin port. What I need is a VHDL project (Quartus) that will implement a custom full duplex parallel to serial design. Development using simulation is fine.

    €16 / hr (Avg Bid)
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    11 bud

    Reading of sensor via PMOD on FPGA Xillinx. More details via messenger Freelancer.com with full requirements.

    €134 (Avg Bid)
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    3 bud

    I need to implement the project using fully parallel interleaver and QPP interleaver in FPGA platform. the language used for coding is Verilog and it is synthesized in Xilinx.

    €132 (Avg Bid)
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    7 bud

    ...for 1 hour work max! We have the attached 128*128 image, i just need some fixes and to run it and produce the new image after the median filter we pass it through microblaze FPGA in the c program. I specifucally want: 1. instead of arrays i want the resulting image to come off like a txt if possible 2. i want inside the code to include the part we

    €19 (Avg Bid)
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    2 bud

    Hello everybody, I want a simple median filter in c embedded through a micriblaze fFPGA. I have some part of the code ready. i need it in 1 hour. If you got it lets talk :)

    €17 (Avg Bid)
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    1 bud

    add memory protection into the operating system, This project needs both hardware and software knowledge, you will be creating / implementing OS functions on the PicoBla...hardware and software knowledge, you will be creating / implementing OS functions on the PicoBlaze, programming in assembler. You may also need to modify the hardware using VHDL.

    €426 (Avg Bid)
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    11 bud

    Hello dear, I have this image table i produced through c embedded median filter code. i want this table to be passed through an FPGA microblaze and then deliver the new image. Thats all. interested? it is for today

    €9 (Avg Bid)
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    1 bud

    Hello dear, I have this image table i produced through c embedded median filter code. i want this table to be passed through an FPGA microblaze and then deliver the new image. Thats all. interested? it is for today

    €9 (Avg Bid)
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    1 bud

    Hello Dear, I have an urgent quick project. I have a...quick project. I have an embedded median filter of a table image 128*128 in c. I have the c code ready already. I just need you to take the median image 8*8 a nd pass it through FPGA with and without cache memory and then deliver the new images we get. It is for today please reply if interested

    €9 (Avg Bid)
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    1 bud

    Hello Freelancers, I would like to pass my table image through a FPGA microblaze (both with cache and without cache) and have a s deliverables the 2 new images we get as results. This is for TODAY. Thank you in advance :)

    €9 - €26
    €9 - €26
    0 bud

    ...guys I will need these simple tasks for $10USD the deadline is today 8 September. Description In C language, i will need embedded a median filter that I need to pass after a FPGA microblaze with image data (128x128) (with and without cache memory). I would like comments on the code and the new resulting image as deliverables. I attach the image table

    €9 (Avg Bid)
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    1 bud

    ...guys I will need these simple tasks for $10USD the deadline is today 8 September. Description In C language, i will need embedded a median filter that I need to pass after a FPGA microblaze with image data (128x128) (with and without cache memory). I would like comments on the code and the new resulting image as deliverables. I attach the image table

    €95 (Avg Bid)
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    1 bud

    ...that I need to pass after a FPGA microblaze with image data (128x128) (with and without cache memory). I would comments on the code and the resulting image as deliverables. 2) I need just a divider in vhdl language to pass through and confirm with numbers that it works. Again comments on the code please. P.S.: 8 by 8 vhdl integer divider I attach the

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    3 bud

    écrire un code vhdl , pour DE0 nano , permettant de lire la température a partir d'une entrée analogique avec un LM19 et en sortie il faut emmètre des son avec un buzzer ( différent fréquence en fonction de la température )

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    ...- $15 USD until 6 or 7 of September. 1) in C language, i will need embedded a median filter that I need to pass after a FPGA microblaze with image data (128x128) (with and without cache memory) 2) I need just a divider in vhdl language to pass through and confirm with numbers that it works I attach the image table in the files section. Thank you

    €24 (Avg Bid)
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    3 bud

    I need help with the structural in Xilinx. I will give you full details. Regards

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    24 bud

    ...i am looking for Electrical & Electronics engineer Mechanical Engineer Civil Engineer Engineers should be expert in following fields Arduino Matlab Raspberry Pi FPGA Verilog/VHDL Python PCB Design (Eagle/Altium) Solidworks AutoCAD if you are expert in any of above mentioned fields then you can place a bid. We will prefer fresh Freelancers but

    €32 (Avg Bid)
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    112 bud

    ...Paride, nice to meet you. i have got your conctact from Alessandro, a classmate. I am working on a easy Vhdl project, i already wrote all the code, the simolulation is working, but i need your help for two fast tasks: • I need to assign the pins on my FPGA, i can't find the correct pin of 2 serial signals. • i need you to check if the clock frequency is

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    1 bud

    Implement an AD2949 IC input block and some more

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    12 bud

    looking for someone who can convert Open CL algorithm into FPGA Verilog project

    €154 (Avg Bid)
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    7 bud

    Only experienced developer in FPGA mining and OpenCL GPU mining. I am looking for a freelancer who can convert Open CL algorithm into FPGA Verilog project.

    €2419 (Avg Bid)
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    15 bud

    ...site. x.25. Electronics Radio Circuits designing and Radio Frequency transmitters and receiver data communication experience required, preferably in Meteor burst technology. FPGA, Microcontroller interfacing, Motorola VHF transceiver experience preferred. The main Aim is Data communication through wireless communication link x.25. VHF Meteor burst transmitter

    €4907 (Avg Bid)
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    11 bud

    ...Testing Video Production Landscape Design Online Writing Financial Analysis Drafting Package Design User Experience Design Moving Swift Autodesk Inventor Tattoo Design Call Center FPGA Handyman Microsoft SQL Server Digital Marketing Wikipedia Zbrush Carpentry Book Artist Procurement Database Development Raspberry Pi Wix VB.NET Sketching Email Developer

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    16 bud

    ...task estimations and time tracking. • Understanding digital electronics and ability to read schematics, analog electronics is a big plus but not obligatory • Experience with FPGA is an asset • Understanding blue prints, engineering drawings and familiarity with PCBs • Experience with measurement instruments (multimeter, oscilloscope). Basic soldering

    €19 / hr (Avg Bid)
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    15 bud

    I want a content writer who knows digital design or digital electronics and vhdl subjects very well.

    €71 (Avg Bid)
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    21 bud

    implement Hough transform algorithm with FPGA with verilog in ISE input = 8*8 binary image

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    2 bud

    ...consulting and code-writing for my FPGA board: [login to view URL] I have 6 PDM mics I got from Adafruit: [login to view URL] I want to do synchronized-recording of the audio from the mics into FPGA-board, and stream this recording to

    €17 / hr (Avg Bid)
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    9 bud

    program with fpga to control TCP data and flow.

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    21 bud

    Hi there! I'm based in Ahmedabad, India. This project is related to lightweight cipher, cryptography. I have attached a pdf containing information relevant to this project w...design so that I can perform power analysis on it. Need the code properly working in two days. I looking for a Clock based implementation on existing design Language used : VHDL

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    4 bud

    Hi there! I'm based in Hyderabad, India. This project is related to cryptography. I have attached a pdf containing information relevant to this project which can be found...clock based design so that I can perform power analysis on it. Need the code properly working in two days. Note: Clock based implementation on existing design Language used : VHDL

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    2 bud

    programing fpga for mining ethereum

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    22 bud

    In this project I need to optimize the code for Groestl miner VCU 1525 to smaller FPGA (Artix-7 XC7A200T). Groestl will be slightly modified and this modification will need to be reflected here. The optimal target speed is 50-70 MHs. (code [login to view URL]) You'll need to adjust the mining program for control and run on

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    ...debugging on ILA/JTAG Preferred Qualifications: - Familiar with AXI interface - Familiar with wireless communication system VLNComm has several current working FPGA projects and one incomplete FPGA project in development on the topic of visible light communication (VLC) system. The projects include two nodes: user and access point (AP). Both parts include

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    27 bud

    Науково-дослідний проект в галузі неруйнівного контролю. ____________________________________________________________ Scientific research project in the field of non-destructive testing.

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    Problem statement: Use an Operating system driven FPGA/Aurdino/Rasberry/ARM(convinient one) hardware to transfer a PDF file to another device via Wi-Fi. Operating system is preferably Linux. It's preferable to have the smallest/ cheapest hardware. The hardware must have the option to integrate Wi-Fi and NFC modules.

    €159 (Avg Bid)
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    9 bud

    Hi there! I'm based in Hyderabad, India. This project is related to cryptography. I have attached a pdf containing information relevant to this project which can be ...individual modules are successfully executing but the final result doesn't appear which you can help me in debugging the same ) Note: Problem in debugging the code Language used : VHDL

    €135 (Avg Bid)
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    9 bud

    Please solve my problem, please teach the solution method and deliver the project file. This project is relevant to FPGA, Ubuntu. My problem is the following. =========================== I want to get image from Pcam 5C from Ubuntu running on ZYBO-Z7-20. First, I cloned this repository,([login to view URL]) and tested pre-built

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    I am the engineering director of VLNComm. We develop the visible light communication system. The system includes an FPGA part. We use Xilinx Vivado as our development platform and Xilinx all programmable SoC as our hardware platform. The project involves transmitter and receiver design. We have implemented 4-PAM (pulse amplitude modulation) and one

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    26 bud

    expert on VHDL is need for a project on digital thermostat. This is a simple task. expert only should bid

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    20 bud

    ... Advance mining strategies 18. Different coins algorithm 19. Windows vs Linux 20. Alt coins mining 21. Exchanges, depths& liquidity 22. New coins and easy to mine coins 23. FPGA 24. Rigs maintenance 25. Pulling the plug 26. Profits strategy, [login to view URL] 27. Basic wallets 28. Shapeshift and cryptonator , alt coins for popular coins -JON 29. Critical success

    €398 (Avg Bid)
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    38 bud

    build a communication block in VHDL at Xilinx environment

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    14 bud