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    3,067 vhdl fpga jobs fundet, i prisklassen EUR

    The parking system has 4 levels, level 1 for admins and disabled, level 2 for staff and disabled, level 3 for visitors and disabled, level 4 for visitors.. we two gates in each level (the gate is a pair of IR sensor) , one gate for entrance and the other for exit.. moreover we have camera and monitor near the entrance gate of level 1 , the camera detects the type of car that entering the parking a...

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    5 bud

    VHDL implemented in altera de2 board

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    3 bud

    Our group wants to implement a game using altera de2 cyclone ii board. Please see the attached file for the details of the game to be implemented.

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    Responsibilities: 1. Engaged in ARM embedded software development (zynq7000 platform development); 2. Debugging WiFi driver and USB driver 3. Build and compile the ke... Build and compile the kernel driver environment 4. Realize the interaction between PS and PL 5. Porting algorithms to embedded platforms (including but not limited to ARM, FPGA, etc.)

    €2143 (Avg Bid)
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    A very simple processor is designed, need to write vhdl codes(few components already written) for it and implement the microprogrammed Control unit.

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    FPGA, VDHL coding 5 dage left
    VERIFICERET

    Please contact me if you expert In FPGA, VDHL coding

    €152 (Avg Bid)
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    10 bud

    The parking system has 4 levels, level 1 for admins and disabled, level 2 for staff and disabled, level 3 for visitors and disabled, level 4 for visitors.. we two gates in each level (the gate is a pair of IR sensor) , one gate for entrance and the other for exit.. moreover we have camera and monitor near the entrance gate of level 1 , the camera detects the type of car that entering the parking a...

    €77 (Avg Bid)
    €77 Gns Bud
    5 bud

    The parking system has 4 levels, level 1 for admins and disabled, level 2 for staff and disabled, level 3 for visitors and disabled, level 4 for visitors.. we two gates in each level (the gate is a pair of IR sensor) , one gate for entrance and the other for exit.. moreover we have camera and monitor near the entrance gate of level 1 , the camera detects the type of car that entering the parking a...

    €156 (Avg Bid)
    €156 Gns Bud
    7 bud

    ...deconding and encoding. this will be run on an MyRIO unit so should either be written for this or easily ported from another DAQ system. Ideally it would utilise the RT Module and FPGA Module and operate with as little overhead as possible. The VI should be able the, in terms of the decoder, output a string or timestamp with the current real time LTC timecode

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    Vhdl is needed

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    How does the parking system work? The p...that i am authorized to park only at level 2 and there is only for example 7 vacant lots for staff in level 2. The system is : FPGA ;Nexys 2 spartan 3E, Camera connected to the FPGA, And the monitor connected via VGA to the FPGA, The gates(pairs of IR sensors) in a bread board as illustrated in the abstract.

    €674 (Avg Bid)
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    3 bud

    Need help program FPGA with Artix-7 using Verliog.

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    I would like a VHDL code that reads 3 txt file and produces 3 txt file. The inputs text files produced by Matlab in binary. please see the attachment for the code I attempted to do but it not working, and text​ input files.

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    ARM firmware with LINUX for DE10-Nano board A. Play with the evaluation board 1. Project Owner will provide a P0496 ARM Processor base on Cyclone V SE FPGA computer board (DE10-Nano board). The board will have Ethernet port and SD card. 2. Developer needs to prepare LINUX Kernel to run on embedded computer board with Ethernet TCP/IP to connect with

    €3717 (Avg Bid)
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    ...with 32 bit instructions and 16 bit data, to be implemented using VHDL. In case of any doubts kindly contact to clarify requirements before making offers. Expectations: - seeking sincere and diligent freelancers. - good understanding and practical experience with digital design using VHDL. - use of Vivado Design Suite (Webpack 2017.4) - aligned and meaningfully

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    Hey, I need help with Verilog / Vivado FPGA project. I'll send you details.

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    1 bud

    Implement the Zen Protocol in the FPGA and update the Mining App

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    Need help program FPGA to communicate with TI7200 through SPI, and generate 300 and 100 Hz sine waves to drive two electric coils,

    €447 (Avg Bid)
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    using VHDL: It’s a simple game of ping pong but only one line using the LED lights. the light will go backward and forward, the player needs to click on control at the edge of last two LED to flip the direction of the LED lights, it will start slow and it will speed up as you play, and the seven segment display will display how many time you hit the

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    Diseño FPGAs en VHDL 18 timer left
    VERIFICERET

    Proyecto enfocado al diseño VHDL sobre FPGAS. Desarrollo de código y de bancos de pruebas, verificación del funcionamiento y resolución de algunas cuestiones. Tiene que estar terminado para el día 17 de diciembre. Se adjunta toda la descripción de lo que hay que hacer, así como unas plantillas para las soluciones y algunos bancos de pruebas...

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    vhdl de 1 board simple project idea

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    VHDL questions Udløbet left

    I have some VHDL questions which I nedd to be solved .

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    FPGA Designing Udløbet left

    Hello, I need FPGA designing expert. I have complete details of the project. Place your bids, i will share the details with the best bidder. Thank you in advance

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    We have an in-house trading application which we intend to move to FPGA, using metamako or solarflare fdk

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    1 bud

    Its a small assignment. If you are an expert and have worked on it before. text me

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    Hi TIV LAbs, I noticed your profile and would like to offer you my project. We can discuss any details over chat. Have you worked on the nexys 4 ddr fpga board?

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    ...minimum resource filter bank in VHDL in the simplest possible way. It can be done on HDL designer or Simulink VIVADO Signal Generator. * Create a word file with short explanations how VHDL model works and add guidelines what algorithm was used to implement DFT. * Do a bit-true simulation in order to confirm that VHDL model works the same as the Simulink

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    PLL in VHDL Udløbet left

    Add in our Design a PLL for variable clock speed

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    ...looking for someone who can design a FPGA based X13bcd miner to mine X13bcd based coins like BCD. The design should be adaptable for possible changes in the X13bcd algorithm. Use vivado or other software make bitstream for vu9p fpga card with pcie,like xilinx vcu1525. make a miner software for ubuntu or windows. FPGA should be capable of mining with

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    The main aim of the project is to design and simulate a Blackjack game model using VHDL and demonstrate it using Alter Cyclone V SoC. The inputs are taken from the player using the switches and push buttons while the output is displayed on the 7-segment display of the FPGA.

    €327 (Avg Bid)
    Fremhævet
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    1. Design platform: VIVADO 18.2 2. Chip: xcz7020CLG484-1 3. language: Verilog 4. Input is all lvds, fclk is frame clockwise, DCLK is data clock, DDR mode Data receives 16 pairs of ADC data. A pair of LVDS DATA inputs 2 channels of ADC data. FCLK is channel A data when it is high and channel B data when it is low. Output data with 32 channel bit width of 12

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    VHDL code for "64-Bit Radix-16 Booth Multiplier Based On Partial Product Array Height Reduction project"

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    Build a VHDL code for 8x8 Wallace multiplier

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    1. Design platform: VIVADO 18.2 2. Chip: xcz7020CLG484-1 3. language: Verilog 4. Input is all lvds, fclk is frame clockwise, DCLK is data clock, DDR mode Data receives 16 pairs of ADC data. A pair of LVDS DATA inputs 2 channels of ADC data. FCLK is channel A data when it is high and channel B data when it is low. Output data with 32 channel bit width of 12

    €132 (Avg Bid)
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    6 bud

    Need to Build the FPGA to HPS DMA code in Arria 10 Intel-Altera FPGA

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    fpga pattern generator connected to a pc starting from an evaluation board and an HDL from TI.

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    Project target is to have a FPGA to communicate with two I2S codecs and to provide a SPI slave connection conveying the I2S data to and from a local MCU. Testing scripts and test timings for the Altera Quartus environment are required. For the proper testing of the project deliverables, test scripts and test timings need to be created and relevant

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    I need to perform video compression using FPGA My final aim is to get a .bit or to .bin file so that I can burn the image to my fpga and simply voila.. Kindly visit this link in order to get an insight to the board that I will be using… [log ind for at se URL] I want video to

    €139 (Avg Bid)
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    Transfer the design of 32x32 bit combination Multiplier and an 8-bit Word Serial Multiplier( using Cadence simulation ) to Visio block diagram and make sure that signal and port are matched.

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    I have my FPGA Xilinx Artix 7 XC7A50T development platform for my personal project. It has DDR3, Hi-speed ADC, Hi-speed DAC, UART, SPI(x2), IIC, and an Ethernet MAC. I need a complete design with microBlaze. I can provide a small example xpr prj but not yet finished. I need someone to configure and link the ip together and have it finally synthesis

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    Need a vhdl expert for Vhdl Code modification. Clock divider and counter design. Code needs to be run on an fpga. Thanks

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    I'm trying to port PYNQ over to a diligent board that is not directly supported. I'm hoping somebody has already done this that would be willing to share their SD card files with me to save me the trouble. I'm looking for PYNQ version 2.2 or 2.3. Please and thankyou.

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    we need an alu of 256*8 memory ..for more information message me

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    D Class Amp Udløbet left

    Design of a D class amp. Digital Input to DAC from FPGA . VHDL files for Digital Input will be provides. Amplification part of the circuit to have a Mosfet setup. DAC and Mosfets have been selected. Full circuit simulation to be done in Tina software.

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    Hello, I have developed the full game in verilog, but I need help with a game over screen to pop up with the player loses all of his lives or a win screen with the player has beaten the game. I will provide you with all the code, mifs, rams, and I just need help to implement the win and game over screens.

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    I have a Circular iterative CORDIC using Fixed-Point​ Arithmetic. code that I would like to change to Dual Fixed Point code in VHDL/ Vivado

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    ProjectDone Udløbet left

    The project is over VHDL using Vivado software, and it contains five smaller parts. have a fun with FPGA and hardware language.

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    12 bud