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    3,712 vhdl code game design vga fpga jobs fundet, i prisklassen EUR

    ...i need a simple program that can calculate time (using hight precision timer, better in micro seconds) between 2 external triggers. Here can be useed FPGA Hardware for example (personaly i prefere FPGA for such task) Frequency range from 0,1 to 100 Hz to be tested. i have programm already done (see attachement), on my laptop i got only value for frequency

    €33 (Avg Bid)
    €33 Gns Bud
    4 bud

    I have the hash algorithm that already implemented in c++ and opencl. I want to convert these hash code into VHDL or verilog.

    €176 (Avg Bid)
    €176 Gns Bud
    1 bud

    I am currently working on some small project need to implement an image processing on FPGA, which may include patterns detection after red color segmentation and recognizing the detected patterns....the image size is 240x240 which has some patterns covered in red color

    €94 (Avg Bid)
    €94 Gns Bud
    4 bud

    This project need to implement the several LVDS interface between Xinix Atix and a sensor buffer This project is completed after simulating transfer (Buffer content ==> FPGA RAM content) This is the testing project, so that, you can get more projects after completing this. If you have experiences, you can complete within a few days. Deliverables:

    €328 (Avg Bid)
    €328 Gns Bud
    4 bud

    hey, I saw your work on the vhdl fm radio and I want to know if you're willing to send that same project.

    €132 (Avg Bid)
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    1 bud

    The project goal is the implementation of a Verilog module to interface a high-speed ADC (250MSps) using DDR. The IO/delay shall be dynamically adjusted after reset thru a test pattern match using a test mode of the ADC. As part of the project a simulation test bench needs to be set-up to verify proper function of the interface.

    €1144 (Avg Bid)
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    15 bud

    ...connected sensors turn (ON or OFF) this EIOD input change to ON/OFF. This ON and OFF state can be show as occupancy of zone or location including coutning. VB NET (interface code available) recommended and Secure and best database to be used. Work procedure: 1. Input sensor (a) connected to EIOD(b) (it has 1 to 8- input). Once input sensor change its

    €1216 (Avg Bid)
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    18 bud

    I have a de1-soc fpga board ([log ind for at se URL]) for the detail. currently i have difficulty id generating code for image processing for my image. I have a completed matlab code that include the image and filtering kernel. I need the code to run into my fpga board.

    €31 (Avg Bid)
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    1 bud

    Need a vhdl project on mips pipelined processor

    €115 (Avg Bid)
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    6 bud

    We're looking for someone with experience is sending data from an FPGA to a PC via a FT601 chip (made by FTDI) and saving the data to a binary file on the PC side.

    €35 / hr (Avg Bid)
    €35 / hr Gns Bud
    8 bud

    an expert on FPGA and Verilog should bid only...

    €137 (Avg Bid)
    €137 Gns Bud
    13 bud

    We would li...minimum 11 inch and HD resolution -Photos must can be downloaded automatically over an internet server(http) -Display must connect photo server over wifi connection, no need any vga hdmi or usb port(There will be wifi modems at same room) -Power must be an cabled adapter -Initial minimum device need is 50(offer for one piece of device)

    €9 - €26
    €9 - €26
    0 bud

    FPGA based VHDL code of control system device, the design should be handwritten, not generating code. The FPGA design must have the std logic data type of the inputs and the outputs and S-Fixed numbers of the entire control design

    €101 (Avg Bid)
    €101 Gns Bud
    6 bud

    FPGA based VHDL code of control system device, the design should be handwritten, not generating code. The FPGA design must have the std logic data type of the inputs and the outputs and S-Fixed numbers of the entire control design.

    €146 (Avg Bid)
    €146 Gns Bud
    7 bud

    Using Altera DE1-SoC FPGA board, I want you to write a code which can do FFT of the provided signal using Quartus II and Modelsim.

    €320 (Avg Bid)
    €320 Gns Bud
    8 bud

    ...(c-9896) to drew the black white picture on paper First, get the picture and manipulate it to make black and white Second, convert the picture to hex decimal and upload it to fpga ( nexys 4 ddr) using matlab Third, control the robot arm to get the pen and drew the picture. the expectation of the project is to have the following: - the required codes

    €2035 (Avg Bid)
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    10 bud

    The brightness measurement with help of PMODALS sensor ([log ind for at se URL] ) should be realized. For this purpose, the Basys 3 FPGA board should be used. Furthermore, an 8051 microcontroller IP core([log ind for at se URL]) is to be used, which takes over the control. The

    €196 (Avg Bid)
    €196 Gns Bud
    6 bud

    Hi Jin, I noticed your work on VHDL/FPGA related projects from your bio. I was wondering if you would like to work on a small project that is based on a FIFO implementation of a FM radio in VHDL. A C++ version of the code is already written, as well as a FIFO and Divider helper files in VHDL. We can discuss any details over chat.

    €141 (Avg Bid)
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    1 bud

    Hi Ahmed, I noticed your work on VHDL/FPGA related projects from your bio. I was wondering if you would like to work on a small project that is based on a FIFO implementation of a FM radio in VHDL. A C++ version of the code is already written, as well as a FIFO and Divider helper files in VHDL. We can discuss any details over chat.

    €176 (Avg Bid)
    €176 Gns Bud
    1 bud

    Hi Ahmed, I noticed your work on VHDL/FPGA related projects from your bio. I was wondering if you would like to work on a small project that is based on a FIFO implementation of a FM radio in VHDL. A C++ version of the code is already written, as well as a FIFO and Divider helper files in VHDL. We can discuss any details over chat.

    €141 (Avg Bid)
    €141 Gns Bud
    1 bud

    Project target is to have a FPGA to communicate with two I2S codecs and to provide a SPI slave connection conveying the I2S data to and from a local MCU. Testing scripts and test timings for the Altera Quartus environment are required. For the proper testing of the project deliverables, test scripts and test timings need to be created and relevant

    €299 (Avg Bid)
    €299 Gns Bud
    6 bud

    This is a long term project to teach and train a software engineer about advanced Electronics, PCB design and FPGA programming. This needs between 3 and 5 hours of face to face (online video conferencing) each week and excellent communication in English. So the payments are weekly as we have the online conferecing calls. The details of what will be

    €38 / hr (Avg Bid)
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    5 bud
    Trophy icon Engineer consultant Business Card 3 dage left

    ...simple one is appreciated or also a simple standard design that represent my work is enough (google image keyword: circuit, pcb, electronic design, firmware, fpga, power electronics ) I would like to have a list of skills that I have on the business card, they are: Power Electronics, Hardware Design, Firmware, Digital Control, Altium, STM32, Batteries

    €40 (Avg Bid)
    Garanteret
    €40
    382 indlæg

    I want to implement YoloV2/V3 custom object detection on FPGA. I have my trained yolo custom object detection files(.cfg and .weights) using darknet and now i want to implement yolo using this files on Xilinx FPGA. I am using ZCU102 and PYNQ evaluation boards with me.

    €669 (Avg Bid)
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    13 bud
    FPGA IP Development Udløbet left

    I need some IPs(PHY/MAC...) for digital communication systems.

    €1082 (Avg Bid)
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    17 bud
    I Need Programmer Udløbet left

    I Need Programmer For FPGA Board & Software Development.

    €2545 (Avg Bid)
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    8 bud

    1- I need someone to design a fully-digital, hardware-based keyboard encoder for a 16-key (4×4) matrix keyboard. 2- The design is to be implemented using an FPGA and verified by both simulation and physical implementation using a development board. 3- You should have Development boards, design software and encoder hardware 4- Separate documents will

    €361 (Avg Bid)
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    ...explaining different aspects of that algorithm. - Explain FPGA developers about Blockchain, cryptocurrency, how crypto-mining works. How to mine that particular algorithm. - Work with them and help them understand how crypto-mining works. And how to mine that perticular algorithm. - Support FPGA developers throughout development. - Must be fluent in

    €14 / hr (Avg Bid)
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    15 bud

    FPGA mining hardware - Xiling FPGA - Nexys Video - Can be leveraged from open source bitcoin miner code. - Based on Verilog. - Provide source code, constraints and full recipe for synthesis, implementation and bitstream generation - Connectivity via JTAG to the host (via USB). May consider UART instead, but as a less desirable solution. Mining software:

    €498 (Avg Bid)
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    8 bud

    I have a VHDL source for the Altera EP3C25F256C8 FPGA design. I like an expert to setup the timing and fitting parameters to give the design optimum performance. I use Quartus II software version 8.1

    €248 (Avg Bid)
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    7 bud

    ...distance measurement with help of MB1010 ultrasonic distance sensor ( [log ind for at se URL] ) should be realized. For this purpose, the Basys 3 FPGA board should be used. Furthermore, an 8051 microcontroller IP core ([log ind for at se URL]) is to be used, which takes over the control

    €240 (Avg Bid)
    €240 Gns Bud
    2 bud

    Your first task is create an EAGLE 7.x library (a symbol and a footprint) for the part (ORT42G5-3BM484C) for it. Part info: Please refer to the attached datasheet file. YOU MUST PROVIDE complete EAGLE 7.x library file. Second task is create an EAGLE 7.x schematic for a breakout board. You can refer the evaluation board schematic. Evaluation board schematic: Please refer to the attached schematic ...

    €220 - €661
    Forseglet
    €220 - €661
    8 bud

    Details are included in the preliminary document. In short, we would lik...separate bids. I may even be posting them as time and material. NOTE: The intention is to eventually take this to a custom SOC implementation with the "link sharing" portion being FPGA programmed in and the rest (SPROC(s) in the doc) running on an ARM with a mcro linux kernel.

    €1310 (Avg Bid)
    NDA
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    11 bud
    FPGA project Udløbet left

    Looking for someone how has knowledge in FPGA programming hardware and software.

    €165 (Avg Bid)
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    16 bud
    FPGA verilog Udløbet left

    Using ModelSim or Quartus II for solving some problems i am working on

    €24 (Avg Bid)
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    17 bud
    Project for Loi L. Udløbet left

    Hi Loi L., I noticed your previous work on the FIFO implementation of a FM Radio in VHDL. I was wondering if you would like to work on that same project. We can discuss any details over chat.

    €132 (Avg Bid)
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    1 bud

    The details of the design will be sent and discussed later. The freelancer needs to have proficient knowledge of VHDL and digital design. Only serious and professional freelancers needed

    €23 (Avg Bid)
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    4 bud
    NEED VHDL CODE Udløbet left

    I NEED VLSI CODE VHDL-7-5-Reed-Solomon ENCODER AND DECODER I HAVE SOME CODE JUST NEED TO RUN AND EXPLAIN MAKING SOME CORRECTIONS

    €14 (Avg Bid)
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    4 bud

    The brightness measurement with help of PMODALS sensor ([log ind for at se URL] ) should be realized. For this purpose, the Basys 3 FPGA board should be used. Furthermore, an 8051 microcontroller IP core([log ind for at se URL]) is to be used, which takes over the control. The

    €159 (Avg Bid)
    €159 Gns Bud
    9 bud

    ...project, a simple VGA (Video Graphics Array) controller shall be implemented using an FPGA Basys3. The VGA controller should be able to display images with a resolution of 640X480 pixels. Furthermore, it should be possible to select between two different images, depending on the position of switch SW1. Document description of whole design including images

    €97 (Avg Bid)
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    2 bud

    Hi, we have project for creating simple RISC processor through vhdl/Verilog. If interested will give more information

    €9 / hr (Avg Bid)
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    1 bud

    VHDL/Verilog basic RISC Processor, will give more details if interested

    €6 / hr (Avg Bid)
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    1 bud

    FPGA based VHDL code of control system device, the design should be handwritten, not generating code. The FPGA design must have the std logic data type of the inputs and the outputs and S-Fixed numbers of the entire control design.

    €207 (Avg Bid)
    €207 Gns Bud
    21 bud

    This project consists to port some c code (around 50 lines) to Verilog in order to run on a FPGA. Output of the contest Verilog .v source file equivalent of verilog.c testbench .v file equivalent to doSimulation() You can run the C code with "gcc main.c && ./[log ind for at se URL]" Elements to select the winning bidder: - Partial screenshot of the impleme...

    €59 (Avg Bid)
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    8 bud

    Hi, I need SPI master design in vhdl. Here is the data sheet. What I need is the functionality to read and write to SPI flash that is in the attached datasheet. I will give you $100 for it if you can successfully complete the project.

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    1 bud
    VHDL & FPGA Design Udløbet left

    Milestone 3: Digital Modulator, Error Block and Digital Demodulator Information often has to be transmitted from one location to another such that it is correctly received despite being sent through a noisy environment that could introduce errors. To achieve this a Digital Modulation Scheme can be used where specific modulation I & Q waveforms are then used to represent each of the four possib...

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    4 bud

    I need a detailed video tutorial which includes the following material: - A tho...Generator" and 3. showing the results on the oscilloscope. The video tutorial should be at least 1 hour. All files and scripts should be shared. The project should be done in VHDL code. The whole procedure must be done in details and questions must be answered clearly.

    €214 (Avg Bid)
    NDA
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    5 bud