Vhdl and verilogJobs
Hi, I have written an SDRAM controller (for a Micron SDRAM) which does not work very well. In the other hand, I have its model (downloaded from Micron's website). I need someone who can write a testbench to verify my controller using Micron's model and fix my controller.
You have to programming a stopwatch with an Memory function in VHDL. It has to run on a Nexy 4 - fpga Board. Best regards, Kevin
Hello, I am looking for Vivado expert. Only bid experts in C/Python/Verilog Hope don't waste time. Thanks
Hi I am looking for RTL SV code for a parameterized mux which takes in input size and select line size accordingly both for one-hot coded and priority coded and it should be synthesizable.
Development of a Fpga-miner and the Host mining App. The communication between FPGA and Host App is USB. Details we can discuss in private chat
...playing field, and we are currently looking for a new mate/co-worker who can detect problems quickly, learn new technologies fast, and participate in designing processors with enthusiasm. WE OFFER: - Opportunity to work with RISC-V, computer architecture of the future - Working on innovative IoT processors and unique processor optimization technology - Participation in the whole development process from analysis to deployment - Collaboration with the world’s top high-tech companies such as Rambus, Microsemi, Analogix, Dongwoon, etc. - Keeping in touch with the latest trends in the industry - Opportunity to work with experienced developers - Possibility to work closely with other teams - Receptivity to your own innovations and ideas - A young and...
I need someone having expertise in verilog to enhance a processor design to carry out more instructions using Quartus prime software. Further details will be provided. Deadline 3 days. Thanks
Development of a Fpga-miner and the Host mining App. The communication between FPGA and Host App is USB. Details we can discuss in private chat
The goal of the project is to translate an LCD bus with propriety signaling to driv...timing chart of source. Output LCD + LCD controller datasheet + init code will be provided. Development board will NOT be provided (you should have your own). VHDL is preferred but not obligatory, Verilog can also be used. Altera family devices should be used. Project should be oriented towards low power and low cost since day 1. Information about further requirements (some software features) will be provided later. Please read this before quoting. Please do not quote if you can not complete this project. Please make sure this is something you are able to complete within less than 30 days. The project is not very complicated and should be moderate difficulty for someone wi...
Looking for vhdl expert for Blockchain field. It must familiar with python too. Will give more detail via interview.
- Need to develop bitstream for different algorithm for FPGA boards. - Developer with proven experience with FPGA Verilog. - Can able to code, simulate, synthesize and compile verilog on FPGA. - Would be great if understands concept of Blockchain technology and how it works. - Understand requirements and based on that able to prepare hardware requirements, specs of FPGA, plan and execute development. - Ability to explain code, work with in-house team for hardware configuration and to compile code to FPGA. So above average communication skills required. - Need to sign NDA and Ownership agreement.
Looking for an experienced programmer in Lattice FPGA's, specifically the ICE40 series. Simple project, buffer 320 bytes of data with multiple clock domains. Prefer VHDL
I have a VHDL code. Then It has some issue. I need to fix it within a few hours. If you are electronic expert you can do it within 1 hours. I'll send details via interviewing. Ivan.
I need you to develop a Vhdl or Verilog program for image similarity search, by using locality sensitive bloom filter for fpga
I need to convert a python code to vhdl code using myhdl.i will attach the python code.
...stream cipher and to compare it to Grain-128 and Trivium in terms of area, delay, latency and power energy consumption so we can decide which suits us the best. Your tasks will include: • Investigating hardware optimization techniques targeting Xilinx FPGA Devices • Evaluating its speed, throughput, area, power consumption, and energy efficiency and comparing the results to Grain-128 and Trivium. I am looking for a candidate expert on VHDL/Verilog and with a Virtex-5 board to work on ISE 14.7. We will use ModelSim and Xilinx ISE tools in this project. The deliverables will be: a. code b. testbenches c. measurements Notes: 1- Espresso stream cipher is already implemented 2- It is required to compar...
Bug-fix Mining App and FPGA-VHDL Project. You have to fix the mining App what is written in C and running on a Linux server. And fix on the FPGA side the PLL and add multicores.
Tutor/Mentor Required(Online): -- Good knowledge of Embedded c/c++ and VHDL -- Good Experience with Renesas Microcontrollers and e2 Studio
Muktiplexer of 2 to 1 in vhdl using tje software xillinix
more details will be given in the chat only serious expert and my maximum budget for this task is $100
Please read all the details first. and I will create 45% milestone before we start and when its done this task 100% I will create other 60% milestone and released both. I always paid the coder. check my review. ( Dont bid if you are not agree my terms) Hello /////////////////////////////////// ///////////////////////////////// ///////////////////////////// Looking for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you suggest starting wit...
...to develop the implementation of the keccak256 algorithm for FPGA XILINX xcku035-1ffva1156c. Verilog / VHDL development language (Xilinx Vivado Design Suite) Functional check on any available board. Requirements for implementation: 1. The algorithm should work in accordance with ; a. The source can be taken as MVis-tokenminer 2.1.17; 2. The basis of the hash function is to take the source code ; a. The keccak256 algorithm should operate at the maximum FPGA frequency xcku035-1ffva1156c; b. The algorithm must use a minimum of LUT; c. The algorithm must use DSP Slices and Block RAM; d. The number of streams (copies of the algorithm) should be limited only by the
Hi somebody needed for find fpga (verilog-vhdl) remote projects I paid 20% commission for each project
Hi,eveyone.I need a signal processing coding for my work using altra quartus II and VHDL.
Implementation of 4 bit alu in VHDL using the software Xillinix ISE I Need report on circuits diagrams, truth table, and simulations results the structure report should go by 1-introduction 2-block diagram 3-Technical Words 4-Implementations 5-Results 6-Conclusion
i want a verilog coding regarding radix-4 16 point FFT. so i need expert help.
I have a VHDL code.. I need someone to explain that code in detail to me.. what stuff it is doing on board..
Please read all the details first. and I will create 45% milestone before we start and when its done this task 100% I will create other 60% milestone and released both. I always paid the coder. check my review. ( Dont bid if you are not agree my terms) Hello /////////////////////////////////// ///////////////////////////////// ///////////////////////////// Looking for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you suggest starting wit...
Hi Ahmed M., Write VHDL code for frequency comparison on threshold base after the FFT_64 block in my code, the threshold will be defined by user through VIO or uart. The results should be verified on ILA in Hz. Also comment every line of code.
Please read all the details first. and I will create 45% milestone before we start and when its done this task 100% I will create other 60% milestone and released both. I always paid the coder. check my review. ( Dont bid if you are not agree my terms) Hello /////////////////////////////////// ///////////////////////////////// ///////////////////////////// Looking for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you suggest starting wit...
Please read all the details first. and I will create 40% milestone before we start and when its done this task 100% I will create other 60% milestone and released both. I always paid the coder. check my review. ( Dont bid if you are not agree my terms) Hello /////////////////////////////////// ///////////////////////////////// ///////////////////////////// Looking for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you suggest starting wit...
Please read all the details first. and I will create 40% milestone before we start and when its done this task 100% I will create other 60% milestone and released both. I always paid the coder. check my review. ( Dont bid if you are not agree my terms) Hello /////////////////////////////////// ///////////////////////////////// ///////////////////////////// Looking for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you suggest starting wit...
Please read all the details first. and I will create 40% milestone before we start and when its done this task 100% I will create other 60% milestone and released both. I always paid the coder. check my review. ( Dont bid if you are not agree my terms) Hello /////////////////////////////////// ///////////////////////////////// ///////////////////////////// Looking for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you suggest starting wit...
Initial Milestone : Write VHDL code for frequency comparison on threshold base after the FFT_64 block in my code, the threshold will be defined by user through VIO or uart. The results should be verif on ILA
Please read all the details first. and I will create 40% milestone before we start and when its done this task 100% I will create other 60% milestone and released both. I always paid the coder. check my review. ( Dont bid if you are not agree my terms) Hello /////////////////////////////////// ///////////////////////////////// ///////////////////////////// Looking for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you suggest starting wit...
Please read all the details first. and I will create 40% milestone before we start and when its done this task 100% I will create other 60% milestone and released both. I always paid the coder. check my review. ( Dont bid if you are not agree my terms) Hello /////////////////////////////////// ///////////////////////////////// ///////////////////////////// Looking for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you suggest starting wit...
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Hi Ahmed M., I noticed your profile and would like to offer you my project. We can discuss any details over chat. I'm a friend of Alessandro that contact you for a mini project of VHDL
Hello That I want is a basic uart communication with fifo buffer I have a small code ready At last I want a small call for explain
hi all how are you? this is a verilog question whats output base on testbench? the codes are in txt file
Need to implement 16 point FFT in Verilog (Xillinx) , and use memory based LUT optimization , using the research paper attached to optimize the 16 point FFT, and compare the Area and Timing of both the optimized and un-optimized implementation. Will need a small write-up comparing both the results , complete source code of both the implementations.
I want SPI master in VHDL for writing and reading from flash IS25WP032
I need urgent work requires Verilog expertise. It also includes a short report. More details on chat.
I need to design a 4 bit adder in verilog. I will provide more details in the chat.
...focuses on the use of VHDL language to describe a simple design and to verify its correct operation through test benches and simulations. The implementation on a specific FPGA has to allow also to obtain additional information of consumption, frequency of operation, etc. In short, it is a matter of following a design process as close to the real as possible, but in a controlled environment with a simple design. Requirements • To know the general characteristics and tools involved in the design process of a specific application integrated circuit (ASIC), specifically a FPGA. • Know how to implement logical functions in programmable logical devices using description languages of Hardware, in particular, VHDL. • Know how to design on FPGA...