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    4,859 verilog ascii jobs fundet, i prisklassen EUR
    Verilog project FSM Udløbet left

    Verilog project FSM Verilog project FSM Verilog project FSM

    €10 / hr (Avg Bid)
    €10 / hr Gns Bud
    1 bud

    Hey, I have a project that needs to be done in Verilog and Vivado and I'll share details to anyone interested.

    €22 (Avg Bid)
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    8 bud
    Verilog Task on Nexys 4 board 5 dage left
    VERIFICERET

    Just need to design the Snake Gane as per my specifications. I am using Nexys 4 development board.

    €46 (Avg Bid)
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    5 bud

    This is a project in extension to an open source github pro...we control. Deliverables are: (1) a simple webpage with cookies taht contain a stort string of ASCII-based characters (2) python code to get the loaction of the cookies for a current version of IE, Edge, Firefox and Chrome and (3) python code to read ASCII content (string) from the cookies.

    €26 (Avg Bid)
    €26 Gns Bud
    4 bud

    Snake Game : 1.) Should run on Altera DE2 Board or on basy3 . 2.) Should Support VGA. 3.)Needed in a 3 days. skills:- verilog software:vivado i need this project in verilog and not in VHDL

    €68 (Avg Bid)
    €68 Gns Bud
    5 bud

    Task on verilog 3 bit ALU Deadline 1 day Amount USD 40

    €55 (Avg Bid)
    €55 Gns Bud
    22 bud

    Need a small task on 3 bit ALU using verilog. Deadline 18 hours amount usd 30 .

    €24 (Avg Bid)
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    3 bud
    Distance using FPGA Udløbet left

    I work in the Electrical Engineering Field. The project is to create a distance measuring program using verilog. I will be using Basys 3 ( FPGA) and an Ultrasonic sensor ( HC-SR04). The idea is to measure the gap between two vehicles. The sensor will be placed in the front of a toy car and used to measure the gap instantaneously and also save that data

    €102 (Avg Bid)
    €102 Gns Bud
    21 bud

    I have a small piece of code that reads in an ASCII Autocad dxf file. This needs to be read into an array of structs where the struct is an Int and a String. For small files the way this is implemented is fine. But for large files, ~12.4 GB, it grinds to a halt taking about half an hour as the amount of memory required explodes to ~75 GB. Looking for

    €26 (Avg Bid)
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    1 bud

    I would like to discuss with freelancers having strong expertise in programming languages like VHDL, Verilog, Matlab, embedded C Please reach out to me. Engineering B.Tech. is must

    €14 / hr (Avg Bid)
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    30 bud

    ...STM32F103 and STP16CPC26XTR (16 channels led driver controller) The software can receive information via RS485 (serial port) and CAN BUS. You can receive 5 frames: Left Text (5 ASCII char) (5 bytes) Right Text (5 ASCIIchar) (5 bytes) State of linear bar, state of curved bar and state of arrows and central LEDs (2 Bytes) Brightness level (1 Byte). General

    €25 (Avg Bid)
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    5 bud

    I have project ready already just need some help!

    €169 (Avg Bid)
    €169 Gns Bud
    9 bud

    Hi guys, I've done a simple design to test the SRAM of Digilent Cmod A7 FPGA board. This is how it works: Using a terminal through UART, I send the input data and address to the SRAM. Then I send address where to read, and I get back the data previously written. Everything works OK except the controller. I need someone to review my design and fix it.

    €17 (Avg Bid)
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    6 bud

    We manufacture hardw...program will need to be able to identify local ports (on PC or PI), choose communications settings and open ports for communications. We need to be able to send commands (in ASCII) and receive responses through buffers that we can further process or store. We'd like to have a common code base (PC and PI) that we can build upon.

    €519 (Avg Bid)
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    35 bud

    I have 9 pairs of characters let's say 1g 3d 5f zz 90 00 00 3e 11 I need to do the...designated cell but if it was 2d instead to type jhon instead of Mark. 3. If the 2nd pair is 59 to type "carpenter" 4. If the 4th pair is 7h then Type the equivlant value in Ascii. Doing it in Visual Basic is possible as well. I need the source code as well please.

    €65 (Avg Bid)
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    38 bud

    I am looking a basic PHP script to connect a cricket bowling machine on serial port and operate via PHP script. I provide all ASCII based commands.

    €180 (Avg Bid)
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    20 bud

    Any encryption code (AES/RSA) written in VHDL/Verilog in Quartus II for fpga board stratix IV. Please contact for more details.

    €29 (Avg Bid)
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    3 bud

    I need a libreoffice-writer extension/addon that, based on the number provided in a.x.y.z format builds me a frame, inside which a non-ascii set of characters are inserted and displayed in the middle of editing a libreoffice writer document. These utf-8 strings would be pulled from a dictionary (or a database) uploaded by the coder, in the given extension

    CSS
    €18 - €146
    €18 - €146
    0 bud

    we need a technical content writer who knows the system Verilog, OVM and UVM.

    €122 (Avg Bid)
    €122 Gns Bud
    7 bud

    This is pavan. I am from the VLSI industry. I need a technical writer to explain 3 subjects(digital electronics, Verilog, and VHDL).

    €105 (Avg Bid)
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    17 bud

    (1)Key generation. (2...a sentence, convert it to ASCII codes, divide it into blocks, encrypt each block with the round keys, and output the ciphertext of the sentence. (iii)For decryption, input the ciphertext (cut/paste), divide it into blocks, decrypt each block with the round keys, convert the plaintext to the sentence on the basis of ASCII codes

    €85 (Avg Bid)
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    5 bud

    We are looking for C++ programmer with experience in building GUI using QT. Preferable EDA/ Verilog Experience with background in Electrical Engineering

    €436 (Avg Bid)
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    15 bud

    Please refer the att...the attached document. This is the base paper of my project. I want to do my project on 64 bit square root carry select adder. I request you to help me with the coding in Verilog using Xilinx in gate level or switch level modelling. Can you please share the cost and the time line for the code. I will need it as soon as possible.

    €37 (Avg Bid)
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    13 bud
    Fix VS2008 program Udløbet left

    We need to fix a program VS2008 program so it will generate an ascii (XML) file the right way. See attachment. Look at [log ind for at se URL] to see how the result should look like after your fix. Need an experience Visual Studio C++ programmer. SQL knowledge

    €163 (Avg Bid)
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    25 bud

    Hi, I need to make a Yugioh game without GUI only through coding. It will be necessary to convert some images to ASCII. .h and .cpp files. Use pointers for Vectors and Char* and do not use STRING.

    €19 - €158
    €19 - €158
    0 bud

    Require a post processor to take Velodyne LiDAR point cloud data (PCAP format) in the scanners coo...format) in the scanners coordinate system (SOCS) and convert to real world coordinates provided from a SBet (Smoothed Best Estimate of Trajectory) from the GPS/INS system (ASCII text). The data would be output in LAS format. Both files are time tagged.

    €1006 (Avg Bid)
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    10 bud

    ...pull && /pups/bin/pups --stdin Already up-to-date. I, [2018-09-23T06:07:01.258185 #14] INFO – : Loading --stdin /pups/lib/pups/[log ind for at se URL]:in split': invalid byte sequence in US-ASCII (ArgumentError) from /pups/lib/pups/[log ind for at se URL]:inrun’ from /pups/bin/pups:8:in `’ 7bfaa7cccfa02ecadea2fc89e6ee2d54c5f813f8070f57d1babe4e40c688dee8 ** ...

    €32 (Avg Bid)
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    4 bud

    Front End VLSI Design engineer Part Time in Bangalore Looking for expert FPGA Design engineer with RTL Design [Verilog] Proven track record of designing, developing, prototyping, and testing high speed FPGA designs Experience in Verilog programming & experience with Xilinx devices and development tools Design Simulation experience [Modelsim] Candidate

    €153 (Avg Bid)
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    12 bud

    Front End VLSI Design engineer Part Time in Bangalore Looking for expert FPGA Design engineer with RTL Design [Verilog] Proven track record of designing, developing, prototyping, and testing high speed FPGA designs Experience in Verilog programming & experience with Xilinx devices and development tools Design Simulation experience [Modelsim] Candidate

    €130 (Avg Bid)
    €130 Gns Bud
    4 bud

    The aim of the project is to design a BIST controller to insert and detect the faults (defect) like ...Read disturbance, Erase disturbance, Program disturbance, SAF, TF, ADF, CFs, TF, NPSF, Retention fault in FLASH memory by using BIST algorithm like March algorithm using verilog or VHDL in Xilinx or Modelsim. Need Simulation waveforms for the same.

    €360 (Avg Bid)
    €360 Gns Bud
    2 bud

    ...pot. Use printf() over USB to output 3 groups of data: Generator data, Meter' results at threshold level and on-chip temperature ( ADC1_IN16 ) and Vbat ( ADC1_IN18 ), all in ASCII format as in this example: "Generator data:n" "Amplitude 3.0v Frequency 100Hz Duty Cycle 50% n" "Measurement data at Threshold 50% 1.65V n" "Amplitude 1.65v F...

    €2454 (Avg Bid)
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    12 bud

    i have a sdk for time attendance device. so can u check it how it acept the data from it ,(binary) and make same script in php (u n...sdk for time attendance device. so can u check it how it acept the data from it ,(binary) and make same script in php (u need just the part that get binary and convert to ascii) can u connect via team viewer and see

    €27 (Avg Bid)
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    4 bud
    CHECK sdk and Udløbet left

    i have a sdk for time attendance device. idk in which language it is, i thik is asp net or c# idk,, so can u check it how it acept the data from it ,(binary) and make same... i thik is asp net or c# idk,, so can u check it how it acept the data from it ,(binary) and make same script in php (u need just the part that get binary and convert to ascii)

    €52 (Avg Bid)
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    1 bud

    i have a sdk for time attendance device. so can u check it how it acept the data from it ,(binary) and make same script in php (u need just the part that get binary and ...sdk for time attendance device. so can u check it how it acept the data from it ,(binary) and make same script in php (u need just the part that get binary and convert to ascii)

    €22 (Avg Bid)
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    6 bud

    ...php i cant get the binary , coz i see strange characters, few developer tried and they were not able to get it in php so is there a way to get that binary and convert to ascii or whatever u like and then save to a file or send to php or whatever, so i just want to recive binary and decode so i can see what info is there p.s HTTP request Content-type

    €56 (Avg Bid)
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    9 bud
    DSP48E1 help Udløbet left

    Hi! I need some help with DSP48E1 verilog instantiation.

    €3 / hr (Avg Bid)
    €3 / hr Gns Bud
    5 bud

    Need to create an INVOICES AND CREDIT NOTES FILE with FACTORS from Sage 50 Accounts ASCII character format.. The file must be in ASCII character format and must have a record length of 550 characters. It must consist of batches each containing a batch header and up to 999 batch items.

    €157 (Avg Bid)
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    7 bud
    I want clients Udløbet left

    I need some help with selling my services. I am verilog/ matlab coder and I need customers . you find me a client , I write his/her code and you get paid %30 of the project budget

    €16 (Avg Bid)
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    2 bud

    Need to create an INTERFACE FILE GUIDELINE with FACTORS from sage in ASCII character format.

    €135 (Avg Bid)
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    3 bud

    I need to implement the project using fully parallel interleaver and QPP interleaver in FPGA platform. the language used for coding is Verilog and it is synthesized in Xilinx.

    €132 (Avg Bid)
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    7 bud

    ...we want is either WordPress (WooCommerce) or PrestaShop. - Payment gateways should either be PayPlug, Stripe, or Braintree. - The file format for 3D cad files is .stl (both ASCII and binary formats) and also STEP files eventually, but not in the first release. Main Features - The website layout should be responsive while simple, fitting in a technical

    €7989 (Avg Bid)
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    75 bud

    ...i am looking for Electrical & Electronics engineer Mechanical Engineer Civil Engineer Engineers should be expert in following fields Arduino Matlab Raspberry Pi FPGA Verilog/VHDL Python PCB Design (Eagle/Altium) Solidworks AutoCAD if you are expert in any of above mentioned fields then you can place a bid. We will prefer fresh Freelancers but

    €33 (Avg Bid)
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    110 bud

    Features: 1). read every ip segment from ascii format file 2). translate ip segment to every ip address 3). save every ip address to output ascii file Example: 1). [log ind for at se URL] (input file) 192.168.1.0-[log ind for at se URL] 192.169.1.0-[log ind for at se URL] 5.5.5.0-5.5.3.58 2).[log ind for at se URL] (output file) [log ind for at se URL] [log ind for at se URL] [lo...

    €9 - €17
    €9 - €17
    0 bud
    verilog project Udløbet left

    verilog coding using putty or terminal. if you are interested i will give more information.

    €118 (Avg Bid)
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    27 bud
    System verilog Udløbet left

    I want help with system Verilog coding. I have a working code that I want revised a bit.

    €85 (Avg Bid)
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    8 bud

    I need some changes to an existing website. Convert existing website to have ascii text files as the values if drop down lists

    €104 (Avg Bid)
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    20 bud

    ...my exe program taken all tcp or upd protocol from server[all protocol coming gps navigation need just open all port only] by our software system [software already have ascii and hex decode] and post it a all value in a proper server page .[page build by php no need code on php just send all data by get method on a proper server page only]. need

    €170 (Avg Bid)
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    5 bud
    verilog project Udløbet left

    mtech Verilog project

    €18 (Avg Bid)
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    19 bud

    Write an extension, that, based on the number provided in a.x.y.z format builds me a frame, inside which a non ascii set of characters are inserted and displayed in the middle of editing a libreoffice writer document. These utf-8 strings would be pulled from a dictionary (or a database) uploaded by the coder, in the given extension.

    €91 (Avg Bid)
    €91 Gns Bud
    3 bud

    looking for someone who can convert Open CL algorithm into FPGA Verilog project

    €157 (Avg Bid)
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    7 bud