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    341 project vlsi design jobs fundet, i prisklassen EUR

    sir my project is fir filter design and implementation on FPGA VLSI .

    €128 (Avg Bid)
    €128 Gns Bud
    1 bud
    VLSI Expert -- 5 Udløbet left

    Use Synopsys PrimeTime and PT-PX for timing and power analysis. more details provided in interview. Write some TCL scripts for a software and leave them in the server where the software is installed, as well as all the output reports that result of running those scripts in the server. To access this server employer gave me user/pass. The other requierement was to write the report.

    €222 (Avg Bid)
    €222 Gns Bud
    1 bud
    NEED VHDL CODE Udløbet left

    I NEED VLSI CODE VHDL-7-5-Reed-Solomon ENCODER AND DECODER I HAVE SOME CODE JUST NEED TO RUN AND EXPLAIN MAKING SOME CORRECTIONS

    €14 (Avg Bid)
    €14 Gns Bud
    4 bud
    VLSI Expert -- 4 Udløbet left

    Use Synopsys PrimeTime and PT-PX for timing and power analysis. more details provided in interview. Write some TCL scripts for a software and leave them in the server where the software is installed, as well as all the output reports that result of running those scripts in the server. To access this server employer gave me user/pass. The other requierement was to write the report.

    €222 (Avg Bid)
    €222 Gns Bud
    2 bud
    VLSI Expert -- 3 Udløbet left

    Use Synopsys PrimeTime and PT-PX for timing and power analysis. more details provided in interview.

    €177 (Avg Bid)
    €177 Gns Bud
    1 bud
    vlsi expert -- 2 Udløbet left

    Use Synopsys PrimeTime and PT-PX for timing and power analysis. more details provided in interview.

    €27 - €222
    €27 - €222
    0 bud
    VLSI Expert Udløbet left

    Use Synopsys PrimeTime and PT-PX for timing and power analysis. more details provided in interview.

    €244 (Avg Bid)
    €244 Gns Bud
    2 bud
    VLSI Project -- 3 Udløbet left

    Use Synopsys PrimeTime and PT-PX for timing and power analysis. Check the following link. [log ind for at se URL]

    €137 (Avg Bid)
    €137 Gns Bud
    2 bud
    A vlsi design Udløbet left

    magic design on ubuntu where you can build

    €23 (Avg Bid)
    €23 Gns Bud
    1 bud
    VLSI design Udløbet left

    I need to design VLSI using magic in Ubuntu.

    €52 (Avg Bid)
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    2 bud

    Here projects are implemented in VHDL programming using Xilinx software. B.E/[log ind for at se URL] Mtech projects would include the kit imple...Tech/M.E/[log ind for at se URL] Mtech projects would include the kit implementation which can be done on sparten series based on the various application. Major projects and mini projects in VLSI for ECE students are done here.

    €120 (Avg Bid)
    €120 Gns Bud
    5 bud

    ...software developer with experience in ARM mbed OS who is helping me with writing the firmware for a project incl. the following components: 1) MCU Nordic nrf52 (Fanstel BT832 or BT840) 2) Gyro incl. DMP (Invensense mpu9250/ICM20689 ) 3) Sound decoder (VLSI vs1053b) 4) Serial (SPI) NAND flash storage (Micron MT29F2G01) 5) Touch input (TI msp430fr I2C)

    €1516 - €3032
    Forseglet NDA
    €1516 - €3032
    35 bud

    I'll provide the circuit with the dimension of transistor, I need a freelancer to do two layout in Lasi7.

    €95 (Avg Bid)
    €95 Gns Bud
    4 bud

    This will be educational institute catering various learning needs of students across various fields of education. Such as one of the example is VLSI verification or software testing etc... Logo should be with name "1-Stop EduHub". Tag line should be "Focused to Deliver Quality Learning". And logo image should be somewhere along the line of attached

    €21 (Avg Bid)
    €21 Gns Bud
    6 bud

    i am student, working on PD in vlsi domain, i need to improve financial ,so in free time I'm quite to write contents

    €35 / hr (Avg Bid)
    €35 / hr Gns Bud
    1 bud

    Hi, I have a problem with my project, I built everything with a problem with one of the bits sum like s0 s1 s2 s3, I am having issue with s2 , it's giving me unknown and I have a carry in which is not identified anyone with a good experience with VLSI should fix it smoothly. I attached IRSIM analyzer photo to illustrate the issue.

    €110 (Avg Bid)
    €110 Gns Bud
    5 bud

    Objective is to develop one VLSI Architecture and Verilog code for Algorithm-1(2D-SRNCP) [1] with Derivative variance correlation map for given two 256*256 synthesized & one SAR real time image. Implementation should be done in Matlab@Simulink and Xilinx@ System Generator environment. Implement above algorithm on FPGA Board & GPU. Simulation results

    €124 (Avg Bid)
    €124 Gns Bud
    2 bud

    Simple CMOS VLSI Design Project (Power, Sequential Timing, Logic Families, Wires & Memory) Look at the problems in: [log ind for at se URL] WILL PAY GENEROUSLY. $$$ Project Description is: [log ind for at se URL] Reference Literature: CMOS VLSI Design Happy Bidding

    €9 - €177
    €9 - €177
    0 bud

    Simple CMOS VLSI Design Project (Power, Sequential Timing, Logic Families, Wires & Memory) MUST BE ACCURATE AND CORRECT. WILL PAY GENEROUSLY. $$$ Project Description is: [log ind for at se URL] Reference Literature: CMOS VLSI Design Happy Bidding

    €244 (Avg Bid)
    €244 Gns Bud
    2 bud

    Simple CMOS VLSI Design Project (Power, Sequential Timing, Logic Families, Wires & Memory) MUST BE ACCURATE AND CORRECT. WILL PAY GENEROUSLY. $$$ Project Description is: [log ind for at se URL] Reference Literature: CMOS VLSI Design Happy Bidding

    €137 (Avg Bid)
    €137 Gns Bud
    1 bud

    I have a Introduction to VLSI Design school course project. I have done most of topics but need to ask a questions and bugs about the project. Need someone to help on this very basic project. Freelancer should known the base sturecture of VLSI lecture. Freelancer either can be student, graduat, postgraduate or more.

    €37 (Avg Bid)
    €37 Gns Bud
    8 bud
    VLSI small Project Udløbet left

    i have some work related to VLSI and i need someone who can do it in efficient way. Should have good command in designing logic circuit designs. should have good knowledge of CMOS, NMOS transistors etc.

    €24 (Avg Bid)
    €24 Gns Bud
    9 bud
    abiramiamanm Udløbet left

    vlsi coding using QUARTUS II software FPGA

    €17 (Avg Bid)
    €17 Gns Bud
    3 bud

    I have 1864 technical words. I want to remove the Plagiarism of this work. Current Plagiarism is 82%. I want plagiarism <20%. I have checked plagiarism at turnitin software. I will check final work plagiarism also at turnitin software. Please the bid only those candidates who can work in my given budget. My budget is 200 (INR) for this work. I attached the same file in the attachments.

    €4 / hr (Avg Bid)
    €4 / hr Gns Bud
    17 bud

    I need someone to create video tutorials for VLSI design from basics to advanced concepts. Advanced Digital Design Concepts CMOS Logic fundamentals RTL Design with Verilog HDL's ASIC Design Systhesis Concepts ASIC Design Stratagies Static Timing Analysis Low power design implementation Design and power Constraints Perl/Shell Scripting ...

    €463 (Avg Bid)
    €463 Gns Bud
    6 bud

    Hi, I have a Flash 6 bits ADC, would like to attempt to make a 12 bits ADC, can you help me to achieve it ?

    €113 (Avg Bid)
    €113 Gns Bud
    15 bud

    This is pavan. I am from the VLSI industry. I need a technical writer to explain 3 subjects(digital electronics, Verilog, and VHDL).

    €110 (Avg Bid)
    €110 Gns Bud
    17 bud

    I need to develop shell script for EDA Tool in VLSI domain

    €74 (Avg Bid)
    €74 Gns Bud
    12 bud

    Front End VLSI Design engineer Part Time in Bangalore Looking for expert FPGA Design engineer with RTL Design [Verilog] Proven track record of designing, developing, prototyping, and testing high speed FPGA designs Experience in Verilog programming & experience with Xilinx devices and development tools Design Simulation experience [Modelsim] Candidate

    €154 (Avg Bid)
    €154 Gns Bud
    12 bud

    Front End VLSI Design engineer Part Time in Bangalore Looking for expert FPGA Design engineer with RTL Design [Verilog] Proven track record of designing, developing, prototyping, and testing high speed FPGA designs Experience in Verilog programming & experience with Xilinx devices and development tools Design Simulation experience [Modelsim] Candidate

    €131 (Avg Bid)
    €131 Gns Bud
    4 bud
    VLSI EDA Cadence Udløbet left

    RISC-V CPU chip high performance low power -- run EDA tools to generate GDSII synthesis and place and route

    €33 / hr (Avg Bid)
    €33 / hr Gns Bud
    14 bud

    Our project relates to vs1005 (All in one audio player on a chip) [log ind for at se URL] by [log ind for at se URL] in combination with the developer board. Programs are written using VLSI Solution's Integrated Development Environment VSIDE [log ind for at se URL] We are coding a VS1005 and want to use a stepper motor

    €115 (Avg Bid)
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    3 bud

    An existing algorithm is available, apply it and get the results. Then make minor changes in it for improvement and get the results

    €54 (Avg Bid)
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    5 bud
    SD Pro Solutions Udløbet left

    ...Engineering and Educational Project provider for Diploma, Engineering (Under Graduate, Post graduates) and Research Scholars. SD Pro was established in the year 2013 for Project Development, Course Designing, Training, and placement guidance, based at South India. SD Pro providers Training and Projects in Embedded systems, VLSI, Matlab, Power systems, Power

    €254 (Avg Bid)
    €254 Gns Bud
    4 bud

    Please find the document in the attachments. Solve the problems step by step with the given data/parameters and please mention all the steps clearly and specify the units for each and every step correctly and make sure the calculation is perfect. For the first question please draw the circuit diagram on a paper and attach it with the solutions and please make sure all the solutions are in WORD doc...

    €78 (Avg Bid)
    €78 Gns Bud
    5 bud

    Based on my current design of CDS active pixel, I'd like to have it extended in order to make an implementation of CMOS Image Sensors of array 512x512 at least. You need to make a proof of concept and make simulations of it. We'll use Cadence Virtuoso 6.17

    €196 (Avg Bid)
    €196 Gns Bud
    6 bud
    Data Collection Udløbet left

    ...data. [log ind for at se URL] If you want to be sure and on the right page to proceed with this project, you can do a sample of 3 colleges - NIT, IIT and any local college and ping me for a check so we can ensure that you are on the right track. • Go to the website of the mentioned

    €118 (Avg Bid)
    €118 Gns Bud
    43 bud
    VLSI Trainer Udløbet left

    We are looking for an experienced Freelancer trainer who can train on VLSI in Bangalore. The curriculum will be provided by the company for the same.

    €681 (Avg Bid)
    €681 Gns Bud
    11 bud

    Hello, I have made a SAR 8 bits binairy coded ADC using method of 2 steps Successive Approximation, but it is a bit buggy. I need very experienced engineer in this field, otherwise it would just be loosing time. The simulation must be done in Cadence Virtuoso 6.x Thanks !

    €35 (Avg Bid)
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    2 bud

    Design and optimization of low power VLSI circuits for Leakage power reduction using Clock Gating with GSA

    €173 (Avg Bid)
    €173 Gns Bud
    4 bud

    ...tracking device for a specific application. I am seeking a solution that is an android and IOS application that is designed to track and locate a sensor (IOT, GPS, RF or other VLSI) technology that is embedded within a projectile that is no larger than 1.68-inches (42.7mm) in width, height and length. The IOS and Android applications should be able to

    €285 (Avg Bid)
    NDA
    €285 Gns Bud
    19 bud
    TCL automation VLSI Udløbet left

    I want to parse a log file and use regexp to filter some patterns and put them in output log file. I have the script. 1- put the -p and -ig inside text files and feed it to code. like this: [log ind for at se URL] -i [log ind for at se URL] -o [log ind for at se URL] -p [log ind for at se URL] -ig [log ind for at se URL] [log ind for at se URL] is: warning| info [log ind for at se URL] is: error|...

    €96 (Avg Bid)
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    5 bud

    Design and optimization of low power VLSI circuits for Leakage power reduction using Clock Gating with GSA

    €163 (Avg Bid)
    €163 Gns Bud
    7 bud

    Project description is under: [log ind for at se URL] Will provide a good reference as well.

    €32 (Avg Bid)
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    5 bud

    Sequential Circuit Design Look at the project description, zip files have the actual images. Also attached a reference.

    €30 (Avg Bid)
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    5 bud

    Sequential Circuit Design Look at the project description, zip files have the actual images. Also attached a reference.

    €13 - €22 / hr
    €13 - €22 / hr
    0 bud

    I need help in VLSI coding language, micro controller , C++ and C

    €375 (Avg Bid)
    €375 Gns Bud
    8 bud

    Vlsi project on excel

    €20 (Avg Bid)
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    4 bud