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    314 project vlsi design jobs fundet, i prisklassen EUR

    Hi, I have a Flash 6 bits ADC, would like to attempt to make a 12 bits ADC, can you help me to achieve it ?

    €107 (Avg Bid)
    €107 Gns Bud
    16 bud

    This is pavan. I am from the VLSI industry. I need a technical writer to explain 3 subjects(digital electronics, Verilog, and VHDL).

    €105 (Avg Bid)
    €105 Gns Bud
    17 bud

    I need to develop shell script for EDA Tool in VLSI domain

    €69 (Avg Bid)
    €69 Gns Bud
    13 bud

    Front End VLSI Design engineer Part Time in Bangalore Looking for expert FPGA Design engineer with RTL Design [Verilog] Proven track record of designing, developing, prototyping, and testing high speed FPGA designs Experience in Verilog programming & experience with Xilinx devices and development tools Design Simulation experience [Modelsim] Candidate

    €152 (Avg Bid)
    €152 Gns Bud
    12 bud

    Front End VLSI Design engineer Part Time in Bangalore Looking for expert FPGA Design engineer with RTL Design [Verilog] Proven track record of designing, developing, prototyping, and testing high speed FPGA designs Experience in Verilog programming & experience with Xilinx devices and development tools Design Simulation experience [Modelsim] Candidate

    €129 (Avg Bid)
    €129 Gns Bud
    4 bud
    VLSI EDA Cadence Udløbet left

    RISC-V CPU chip high performance low power -- run EDA tools to generate GDSII synthesis and place and route

    €32 / hr (Avg Bid)
    €32 / hr Gns Bud
    14 bud

    Our project relates to vs1005 (All in one audio player on a chip) [log ind for at se URL] by [log ind for at se URL] in combination with the developer board. Programs are written using VLSI Solution's Integrated Development Environment VSIDE [log ind for at se URL] We are coding a VS1005 and want to use a stepper motor

    €112 (Avg Bid)
    €112 Gns Bud
    3 bud

    An existing algorithm is available, apply it and get the results. Then make minor changes in it for improvement and get the results

    €53 (Avg Bid)
    €53 Gns Bud
    5 bud
    SD Pro Solutions Udløbet left

    ...Engineering and Educational Project provider for Diploma, Engineering (Under Graduate, Post graduates) and Research Scholars. SD Pro was established in the year 2013 for Project Development, Course Designing, Training, and placement guidance, based at South India. SD Pro providers Training and Projects in Embedded systems, VLSI, Matlab, Power systems, Power

    €248 (Avg Bid)
    €248 Gns Bud
    4 bud

    Please find the document in the attachments. Solve the problems step by step with the given data/parameters and please mention all the steps clearly and specify the units for each and every step correctly and make sure the calculation is perfect. For the first question please draw the circuit diagram on a paper and attach it with the solutions and please make sure all the solutions are in WORD doc...

    €76 (Avg Bid)
    €76 Gns Bud
    5 bud

    Based on my current design of CDS active pixel, I'd like to have it extended in order to make an implementation of CMOS Image Sensors of array 512x512 at least. You need to make a proof of concept and make simulations of it. We'll use Cadence Virtuoso 6.17

    €191 (Avg Bid)
    €191 Gns Bud
    6 bud
    Data Collection Udløbet left

    ...data. [log ind for at se URL] If you want to be sure and on the right page to proceed with this project, you can do a sample of 3 colleges - NIT, IIT and any local college and ping me for a check so we can ensure that you are on the right track. • Go to the website of the mentioned

    €111 (Avg Bid)
    €111 Gns Bud
    46 bud
    VLSI Trainer Udløbet left

    We are looking for an experienced Freelancer trainer who can train on VLSI in Bangalore. The curriculum will be provided by the company for the same.

    €664 (Avg Bid)
    €664 Gns Bud
    11 bud

    Hello, I have made a SAR 8 bits binairy coded ADC using method of 2 steps Successive Approximation, but it is a bit buggy. I need very experienced engineer in this field, otherwise it would just be loosing time. The simulation must be done in Cadence Virtuoso 6.x Thanks !

    €35 (Avg Bid)
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    2 bud

    Design and optimization of low power VLSI circuits for Leakage power reduction using Clock Gating with GSA

    €168 (Avg Bid)
    €168 Gns Bud
    4 bud

    ...tracking device for a specific application. I am seeking a solution that is an android and IOS application that is designed to track and locate a sensor (IOT, GPS, RF or other VLSI) technology that is embedded within a projectile that is no larger than 1.68-inches (42.7mm) in width, height and length. The IOS and Android applications should be able to

    €275 (Avg Bid)
    NDA
    €275 Gns Bud
    20 bud
    TCL automation VLSI Udløbet left

    I want to parse a log file and use regexp to filter some patterns and put them in output log file. I have the script. 1- put the -p and -ig inside text files and feed it to code. like this: [log ind for at se URL] -i [log ind for at se URL] -o [log ind for at se URL] -p [log ind for at se URL] -ig [log ind for at se URL] [log ind for at se URL] is: warning| info [log ind for at se URL] is: error|...

    €93 (Avg Bid)
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    5 bud

    Design and optimization of low power VLSI circuits for Leakage power reduction using Clock Gating with GSA

    €159 (Avg Bid)
    €159 Gns Bud
    7 bud

    Project description is under: [log ind for at se URL] Will provide a good reference as well.

    €31 (Avg Bid)
    €31 Gns Bud
    5 bud

    Sequential Circuit Design Look at the project description, zip files have the actual images. Also attached a reference.

    €29 (Avg Bid)
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    5 bud

    Sequential Circuit Design Look at the project description, zip files have the actual images. Also attached a reference.

    €13 - €22 / hr
    €13 - €22 / hr
    0 bud

    I need help in VLSI coding language, micro controller , C++ and C

    €365 (Avg Bid)
    €365 Gns Bud
    8 bud

    Vlsi project on excel

    €20 (Avg Bid)
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    4 bud
    magic VLSi Udløbet left

    Sketch a transis...widths to achieve ratio of 1(i.e. equal rising and falling resistances) 2- Use Magic VLSI layout tool to Design your layout of the sized design then use irsim to simulate your design (all combinations of input A,B,C). The report should include the following.  Design document  Testing results  Source code and layout

    €34 (Avg Bid)
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    5 bud
    VLSI homework Udløbet left

    everything is clear in the PDF .................................................................................................................................................................................regards

    €43 (Avg Bid)
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    1 bud

    i need 3 to 4 papers review for the paper with brief explanation which is related to VLSI electronics

    €140 (Avg Bid)
    €140 Gns Bud
    2 bud
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    5 bud

    Build a basic building block of the Carry-Skip adder and test it for functionality in LTSpice. Description is in: [log ind for at se URL] Reference: [log ind for at se URL]

    €24 (Avg Bid)
    €24 Gns Bud
    9 bud

    Aim is to design a successive approximation register based analog to digital converter using cadence tool (any vlsi back end tool)

    €825 (Avg Bid)
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    8 bud
    Logo Design Udløbet left

    ... SBL TECHNOLOGIES is a proven semiconductor and embedded design house in India, with deep focus and network in Indian Defence and production agencies. Setup by an experienced team of engineers from the industry to carry-out research, design, development and manufacturing in the field of VLSI and Embedded systems. PCB services from the initial stage

    €30 (Avg Bid)
    €30 Gns Bud
    20 bud

    VLSI developer expertise enhanced in optimization concepts are required

    €442 (Avg Bid)
    €442 Gns Bud
    7 bud

    ...need a project suggestion for a masters project in VLSI testing and verification using Synopsis EDA tools for sequential circuits, because I have to submit a project proposal. Once a project suggestion seems acceptable, I will need help in finishing the project with desired outputs and compare the same with FPGA implementation. By bid for project...

    €512 (Avg Bid)
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    9 bud
    Vlsi project Udløbet left

    I need some one has background about VLSI

    €78 (Avg Bid)
    €78 Gns Bud
    8 bud

    I need help in my company project (more details will be share with shortlisted candidate) You have to be very good in MIPS assembly language RTL, verilog, and basics VLSI technology to be shortlist you have to solve one MIPS Asm. question (attached below) as soon as possible.

    €839 (Avg Bid)
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    5 bud

    I am going to do my research so I need useful research ideas in electronics, electrical, IT domains and those who have research ideas in VLSI , Embedded systems, Finfet technology, Drones bid me.

    €56 (Avg Bid)
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    14 bud

    Multiplier cell design with the application of 8X8 multiplier, related to VLSI design (very large scale integration). required : some report corrections in chapter 1 and 2 regarding the references and report writing. I have a attached a copy of the report and a paper specifying the corrections.

    €18 (Avg Bid)
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    6 bud
    Suggest a topic Udløbet left

    Looking for project topics in VLSI testing and verification using Synopsis EDA tools and TETRAMAX for sequential circuits. Once a topic has been selected, I would need help in finishing the project with desired outputs. Finally, I would also need an explanation of the functioning after completing the project.

    €365 (Avg Bid)
    €365 Gns Bud
    9 bud

    Multiplier cell design with the application of 8X8 multiplier, related to VLSI design (very large scale integration). required : some report corrections in chapter 1 and 2 regarding the references and report writing. I have a attached a copy of the report and a paper specifying the corrections.

    €20 (Avg Bid)
    €20 Gns Bud
    4 bud
    Write some software Udløbet left

    I need you to develop some software for me. I would like this software to be developed for Windows using Python. floor planning of vlsi module , I have to optimise it using Patrical swarm algorithm , need gui for it It requires 1. formation of model ,i.e placement of [log ind for at se URL] with a big block 2. if there are 4 block within a big block then there

    €160 (Avg Bid)
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    4 bud

    An efficient Glitch power reduction using sequential clock gating in VLSI circuits

    €156 (Avg Bid)
    €156 Gns Bud
    7 bud

    c Integrated Circuit (ASIC) implementation of an N x N array multiplier. The ASIC will be fabricated in AMI 0.5 m CMOS technology available through MOSIS.

    €150 (Avg Bid)
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    2 bud

    c Integrated Circuit (ASIC) implementation of an N x N array multiplier. The ASIC will be fabricated in AMI 0.5 m CMOS technology available through MOSIS.

    €26 - €216
    €26 - €216
    0 bud

    c Integrated Circuit (ASIC) implementation of an N x N array multiplier. The ASIC will be fabricated in AMI 0.5 m CMOS technology available through MOSIS.

    €480 (Avg Bid)
    €480 Gns Bud
    5 bud
    VLSI technologia Udløbet left

    I need you to write a research article . About VLSI technologia

    €33 (Avg Bid)
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    9 bud

    c Integrated Circuit (ASIC) implementation of an N x N array multiplier. The ASIC will be fabricated in AMI 0.5 m CMOS technology available through MOSIS.

    €156 (Avg Bid)
    €156 Gns Bud
    5 bud
    CMOS VLSI PROJECT Udløbet left

    c Integrated Circuit (ASIC) implementation of an N x N array multiplier. The ASIC will be fabricated in AMI 0.5 m CMOS technology available through MOSIS.

    €96 (Avg Bid)
    €96 Gns Bud
    1 bud
    COMS VLSI PROJECT Udløbet left

    NxN array multiplier to be designed using cadence

    €26 - €216
    €26 - €216
    0 bud

    A structural methodolgy for scan based design cells with efficient power dissipation methods

    €26 - €216
    €26 - €216
    0 bud
    vlsi project Udløbet left

    the tool required to be used is l-edit software

    €191 (Avg Bid)
    €191 Gns Bud
    4 bud
    DMDG mosfet Udløbet left

    In this project numerically simulated Dual material Double gate MOSFETs structure through ATLAS device simulator. Analysis and comparative study of the electrical characteristics of DMDG MOSFETs with that of conventional SOI MOSFETs has been done. DMDG MOSFETs has become a important part of VLSI research. An analytical model is developed using ATLAS

    €8 - €20
    €8 - €20
    0 bud