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    1,959 project fpga code jobs fundet, i prisklassen EUR

    I have 1.25 Mbps data on an avalon-ST interface to be transferred to the HPS then to the ethernet port o...ethernet port on DE1-SOC board. The data are on 24 channels of 24bit samples. I need you to explain the work to me in case I need to modify it or change the platform. My project which collects the data is attached. The top-level file is i2s_dsp

    €36 / hr (Avg Bid)
    €36 / hr Gns Bud
    2 bud
    FPGA simple circuit board design 6 dage left
    VERIFICERET

    Circuit board designer required for FPGA board with the following specifications. PCI-Express Xilinx Kintex 7 FPGA 50a VCCINT power to FPGA JTAG port (Possible option of 2 x DDR3 SODIMM RAM Slots)

    €1623 (Avg Bid)
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    13 bud

    FPGA based VHDL code of control system device, the design should be handwritten, not generating code. The FPGA design must have the std logic data type of the inputs and the outputs and S-Fixed numbers of the entire control design.

    €143 (Avg Bid)
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    10 bud

    I have the hash algorithm that already implemented in c++ and opencl. I want to convert these hash code into VHDL or verilog.

    €175 (Avg Bid)
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    1 bud

    I am currently working on some small project need to implement an image processing on FPGA, which may include patterns detection after red color segmentation and recognizing the detected patterns....the image size is 240x240 which has some patterns covered in red color

    €93 (Avg Bid)
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    5 bud

    This project need to implement the several LVDS interface between Xinix Atix and a sensor buffer This project is completed after simulating transfer (Buffer content ==> FPGA RAM content) This is the testing project, so that, you can get more projects after completing this. If you have experiences, you can complete within a few days. Deliverables:

    €330 (Avg Bid)
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    5 bud

    The project goal is the implementation of a Verilog module to interface a high-speed ADC (250MSps) using DDR. The IO/delay shall be dynamically adjusted after reset thru a test pattern match using a test mode of the ADC. As part of the project a simulation test bench needs to be set-up to verify proper function of the interface.

    €1144 (Avg Bid)
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    15 bud

    I have a de1-soc fpga board ([log ind for at se URL]) for the detail. currently i have difficulty id generating code for image processing for my image. I have a completed matlab code that include the image and filtering kernel. I need the code to run into my fpga board.

    €76 (Avg Bid)
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    3 bud

    We're looking for someone with experience is sending data from an FPGA to a PC via a FT601 chip (made by FTDI) and saving the data to a binary file on the PC side.

    €35 / hr (Avg Bid)
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    8 bud

    an expert on FPGA and Verilog should bid only...

    €136 (Avg Bid)
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    13 bud

    FPGA based VHDL code of control system device, the design should be handwritten, not generating code. The FPGA design must have the std logic data type of the inputs and the outputs and S-Fixed numbers of the entire control design

    €91 (Avg Bid)
    €91 Gns Bud
    7 bud

    FPGA based VHDL code of control system device, the design should be handwritten, not generating code. The FPGA design must have the std logic data type of the inputs and the outputs and S-Fixed numbers of the entire control design.

    €133 (Avg Bid)
    €133 Gns Bud
    8 bud

    Using Altera DE1-SoC FPGA board, I want you to write a code which can do FFT of the provided signal using Quartus II and Modelsim.

    €318 (Avg Bid)
    €318 Gns Bud
    8 bud

    ...picture and manipulate it to make black and white Second, convert the picture to hex decimal and upload it to fpga ( nexys 4 ddr) using matlab Third, control the robot arm to get the pen and drew the picture. the expectation of the project is to have the following: - the required codes and software for the chip. - logbook for the trials and errors

    €2022 (Avg Bid)
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    10 bud

    The brightness measurement with help of PMODALS sensor ([log ind for at se URL] ) should be realized. For this purpose, the Basys 3 FPGA board should be used. Furthermore, an 8051 microcontroller IP core([log ind for at se URL]) is to be used, which takes over the control. The

    €195 (Avg Bid)
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    Project for Jin C. Udløbet left

    Hi Jin, I noticed your work on VHDL/FPGA related projects from your bio. I was wondering if you would like to work on a small project that is based on a FIFO implementation of a FM radio in VHDL. A C++ version of the code is already written, as well as a FIFO and Divider helper files in VHDL. We can discuss any details over chat.

    €140 (Avg Bid)
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    1 bud

    Hi Ahmed, I noticed your work on VHDL/FPGA related projects from your bio. I was wondering if you would like to work on a small project that is based on a FIFO implementation of a FM radio in VHDL. A C++ version of the code is already written, as well as a FIFO and Divider helper files in VHDL. We can discuss any details over chat.

    €175 (Avg Bid)
    €175 Gns Bud
    1 bud

    Hi Ahmed, I noticed your work on VHDL/FPGA related projects from your bio. I was wondering if you would like to work on a small project that is based on a FIFO implementation of a FM radio in VHDL. A C++ version of the code is already written, as well as a FIFO and Divider helper files in VHDL. We can discuss any details over chat.

    €140 (Avg Bid)
    €140 Gns Bud
    1 bud

    Project target is to have a FPGA to communicate with two I2S codecs and to provide a SPI slave connection conveying the I2S data to and from a local MCU. Testing scripts and test timings for the Altera Quartus environment are required. For the proper testing of the project deliverables, test scripts and test timings need to be created and relevant

    €297 (Avg Bid)
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    6 bud

    This is a long term project to teach and train a software engineer about advanced Electronics, PCB design and FPGA programming. This needs between 3 and 5 hours of face to face (online video conferencing) each week and excellent communication in English. So the payments are weekly as we have the online conferecing calls. The details of what will be

    €38 / hr (Avg Bid)
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    5 bud
    Trophy icon Engineer consultant Business Card 2 dage left

    I need a p...firmware, fpga, power electronics ) I would like to have a list of skills that I have on the business card, they are: Power Electronics, Hardware Design, Firmware, Digital Control, Altium, STM32, Batteries In the contact area, instead of website logo I would like to have the linkedIn icon On the back I want to have my linkedIn QR code.

    €39 (Avg Bid)
    Garanteret
    €39
    382 indlæg

    I want to implement YoloV2/V3 custom object detection on FPGA. I have my trained yolo custom object detection files(.cfg and .weights) using darknet and now i want to implement yolo using this files on Xilinx FPGA. I am using ZCU102 and PYNQ evaluation boards with me.

    €665 (Avg Bid)
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    13 bud
    FPGA IP Development Udløbet left

    I need some IPs(PHY/MAC...) for digital communication systems.

    €1075 (Avg Bid)
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    17 bud
    I Need Programmer Udløbet left

    I Need Programmer For FPGA Board & Software Development.

    €2527 (Avg Bid)
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    8 bud

    1- I need someone to design a fully-digital, hardware-based keyboard encoder for a 16-key (4×4) matrix keyboard. 2- The design is to be implemented using an FPGA and verified by both simulation and physical implementation using a development board. 3- You should have Development boards, design software and encoder hardware 4- Separate documents will

    €359 (Avg Bid)
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    ...explaining different aspects of that algorithm. - Explain FPGA developers about Blockchain, cryptocurrency, how crypto-mining works. How to mine that particular algorithm. - Work with them and help them understand how crypto-mining works. And how to mine that perticular algorithm. - Support FPGA developers throughout development. - Must be fluent in

    €14 / hr (Avg Bid)
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    15 bud

    FPGA mining hardware - Xiling FPGA - Nexys Video - Can be leveraged from open source bitcoin miner code. - Based on Verilog. - Provide source code, constraints and full recipe for synthesis, implementation and bitstream generation - Connectivity via JTAG to the host (via USB). May consider UART instead, but as a less desirable solution. Mining software:

    €494 (Avg Bid)
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    8 bud

    I have a VHDL source for the Altera EP3C25F256C8 FPGA design. I like an expert to setup the timing and fitting parameters to give the design optimum performance. I use Quartus II software version 8.1

    €247 (Avg Bid)
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    7 bud

    ...distance measurement with help of MB1010 ultrasonic distance sensor ( [log ind for at se URL] ) should be realized. For this purpose, the Basys 3 FPGA board should be used. Furthermore, an 8051 microcontroller IP core ([log ind for at se URL]) is to be used, which takes over the control

    €238 (Avg Bid)
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    2 bud

    ...[log ind for at se URL] Requirements for the BOM: - Component distributor: LCSC and Arrow Electronics is preferred. YOU MUST PROVIDE complete EAGLE 7.x project files, including: 1. Complete schematic, both in native EAGLE 7.x format and PDF 2. Symbol and footprint libraries for all components 3. Complete PCB layout, including native

    €219 - €656
    Forseglet
    €219 - €656
    8 bud

    Details are included in the preliminary document. In short, we would lik...separate bids. I may even be posting them as time and material. NOTE: The intention is to eventually take this to a custom SOC implementation with the "link sharing" portion being FPGA programmed in and the rest (SPROC(s) in the doc) running on an ARM with a mcro linux kernel.

    €1301 (Avg Bid)
    NDA
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    FPGA project Udløbet left

    Looking for someone how has knowledge in FPGA programming hardware and software.

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    16 bud
    FPGA verilog Udløbet left

    Using ModelSim or Quartus II for solving some problems i am working on

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    17 bud

    The brightness measurement with help of PMODALS sensor ([log ind for at se URL] ) should be realized. For this purpose, the Basys 3 FPGA board should be used. Furthermore, an 8051 microcontroller IP core([log ind for at se URL]) is to be used, which takes over the control. The

    €157 (Avg Bid)
    €157 Gns Bud
    9 bud

    In this project, a simple VGA (Video Graphics Array) controller shall be implemented using an FPGA Basys3. The VGA controller should be able to display images with a resolution of 640X480 pixels. Furthermore, it should be possible to select between two different images, depending on the position of switch SW1. Document description of whole design

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    2 bud

    FPGA based VHDL code of control system device, the design should be handwritten, not generating code. The FPGA design must have the std logic data type of the inputs and the outputs and S-Fixed numbers of the entire control design.

    €208 (Avg Bid)
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    21 bud

    This project consists to port some c code (around 50 lines) to Verilog in order to run on a FPGA. Output of the contest Verilog .v source file equivalent of verilog.c testbench .v file equivalent to doSimulation() You can run the C code with "gcc main.c && ./[log ind for at se URL]" Elements to select the winning bidder: - Partial screenshot of the ...

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    VHDL & FPGA Design Udløbet left

    Milestone 3: Digital Modulator, Error Block and Digital Demodulator Information often has to be transmitted from one location to another such that it is correctly received despite being sent through a noisy environment that could introduce errors. To achieve this a Digital Modulation Scheme can be used where specific modulation I & Q waveforms are then used to represent each of the four possib...

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    4 bud

    Hi, I need a quick prototype of an Artix-7 fpga that makes a PCIe to sd card controller (SD host controller/SD bus). Objective is to have a fpga card (working on pcie screamer) recognized as a SD/MMC card reader under windows, I need Windows to recognize/be able to install the windows built-in sd card drivers for the card. I don’t need it to actually

    €170 (Avg Bid)
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    6 bud

    -Tools:Altera Quartus,Modelsim and FPGA. -This Project is divided to two parts:- [log ind for at se URL] and implement a 32 bit architecture pipelined CPU with a single bus for a MIPS computer. Found in figure 1 is a top level view of a single core single bus MIPS CPU. Use Quartus to design the list of components found below in Verilog HDL. 1- Register File (16x

    €276 (Avg Bid)
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    6 bud

    I need to have a high level synthesis c++code to synthesis in vivado for hardware implementation in FPGA.

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    This job is ONLY for experienced FPGA - Verilog Programmers. Apply now if you have developed bitstreams for complex applications using Xilinx or Altera FPGAs. We will match your pay with your current income OR more than that (depends on qualification) + Bonus when you deliver expected results + Opportunity to work from home + Chance to work on exciting

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    FPGA with server Udløbet left

    create a web api connect to the fpga cyclone v (altera de10-standred) , then altera can response to hte request change connect some point with each other.

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    5 bud
    FPGA Programming Udløbet left

    FPGA designer that can code chips for different FPGA aspects

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    7 bud

    Hi, I have written (in Verilog) an SDRAM controller (for a Micron SDRAM) which works perfectly. And I have its model (downloaded from Micron's website). I need someone who can write a testbench to verify my controller (using Micron's model). I just need a basic (but good) verification using Modelsim and Verilog.

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    ...you additional information about each sub-module of the project in order to realize the counter. FOR ALL DETAILS PLEASE CHECK DIGITAL DESIGN. pdf !!! Functional Specification A four-digit counter shall be implemented for the Basys3 FPGA development board. The FPGA used is a Xilinx Artix-7 FPGA (XC7A35T-1CPG236C). An asynchronous high-active reset shall

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    9 bud

    Here projects are implemented in VHDL programming using Xilinx software. B.E/[log ind for at se URL] Mtech projects would include the kit implementation which can be done on sparten series based on the various application. Major projects and mini projects in VLSI for ECE students are done here.

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    5 bud