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    2,328 mips verilog jobs fundet, i prisklassen EUR

    Verilog project FSM Verilog project FSM Verilog project FSM

    €9 / hr (Avg Bid)
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    1 bud

    Front End VLSI Design engineer Part Time in Bangalore Looking for expert FPGA Design engineer with RTL Design [Verilog] Proven track record of designing, developing, prototyping, and testing high speed FPGA designs Experience in Verilog programming & experience with Xilinx devices and development tools Design Simulation experience [Modelsim] Candidate

    €155 (Avg Bid)
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    9 bud

    Front End VLSI Design engineer Part Time in Bangalore Looking for expert FPGA Design engineer with RTL Design [Verilog] Proven track record of designing, developing, prototyping, and testing high speed FPGA designs Experience in Verilog programming & experience with Xilinx devices and development tools Design Simulation experience [Modelsim] Candidate

    €124 (Avg Bid)
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    2 bud

    The aim of the project is to design a BIST controller to insert and detect the faults (defect) like ...Read disturbance, Erase disturbance, Program disturbance, SAF, TF, ADF, CFs, TF, NPSF, Retention fault in FLASH memory by using BIST algorithm like March algorithm using verilog or VHDL in Xilinx or Modelsim. Need Simulation waveforms for the same.

    €353 (Avg Bid)
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    2 bud

    Hi! I need some help with DSP48E1 verilog instantiation.

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    5 bud

    i have a problem with mips assembly language, if you are familiar with that language send me

    €169 (Avg Bid)
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    6 bud

    They are attached. It's three files.

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    3 bud

    I need some help with selling my services. I am verilog/ matlab coder and I need customers . you find me a client , I write his/her code and you get paid %30 of the project budget

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    We have a Spansion Flash S34ML02G100TFI00 in which the binary f...Serial number and Mac-Id need to be written in a binary file so that we can re-flash the device without affecting any of the other functionality. The Flash is controlled by a MIPS MCU. The Bidder who successfully completes this project will be awarded three more very similar projects.

    €73 (Avg Bid)
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    4 bud

    I need to implement the project using fully parallel interleaver and QPP interleaver in FPGA platform. the language used for coding is Verilog and it is synthesized in Xilinx.

    €131 (Avg Bid)
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    7 bud

    Need an experienced programmer who can do basic operation in MIPS. Budget- 35$

    €31 (Avg Bid)
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    4 bud

    Hello, i want a small atm software written in mips assembly language; Really basic software, login, deposit and cash out.

    €85 (Avg Bid)
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    2 bud

    ...i am looking for Electrical & Electronics engineer Mechanical Engineer Civil Engineer Engineers should be expert in following fields Arduino Matlab Raspberry Pi FPGA Verilog/VHDL Python PCB Design (Eagle/Altium) Solidworks AutoCAD if you are expert in any of above mentioned fields then you can place a bid. We will prefer fresh Freelancers but

    €32 (Avg Bid)
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    112 bud

    verilog coding using putty or terminal. if you are interested i will give more information.

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    27 bud

    I want help with system Verilog coding. I have a working code that I want revised a bit.

    €89 (Avg Bid)
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    9 bud

    mtech Verilog project

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    19 bud

    looking for someone who can convert Open CL algorithm into FPGA Verilog project

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    7 bud

    Only experienced developer in FPGA mining and OpenCL GPU mining. I am looking for a freelancer who can convert Open CL algorithm into FPGA Verilog project.

    €2409 (Avg Bid)
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    15 bud

    my company is going to build a website for the asic verification. we need a technical content writer who knows the Verilog, system Verilog,uvm and ovm industry subjects.

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    implement Hough transform algorithm with FPGA with verilog in ISE input = 8*8 binary image

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    2 bud

    ...the mics into FPGA-board, and stream this recording to either SD-card or as some other type of output. I need consulting about the possible output-types, and then the HDL/Verilog coding to do the recording, convert PDM-to-PCM (16 bit) and output all 6 microphones Not sure I will be able to supply a remotely-accessible computer connected to the FPGA+mics

    €17 / hr (Avg Bid)
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    9 bud

    Hello, i need help with an assignment for verilog. Specifically I need to continue with an RISC-V ALU that I am required to make. Then after I am done with the executions, I need to make a Fetch, Decode and Writeback code. We can talk so I can explain more of the files given to us and for any questions. Some is the work that I have done so far. I am

    €112 (Avg Bid)
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    Requirements: - Proficient in Verilog/VDHL and C/C++ - Experienced with Xilinx Vivado - Experienced in debugging on ILA/JTAG Preferred Qualifications: - Familiar with AXI interface - Familiar with wireless communication system VLNComm has several current working FPGA projects and one incomplete FPGA project in development on the topic of visible

    €3776 (Avg Bid)
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    27 bud

    Науково-дослідний проект в галузі неруйнівного контролю. ____________________________________________________________ Scientific research project in the field of non-destructive testing.

    €332 (Avg Bid)
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    3 bud

    Verilog expert required for task on Digital Systems Deadline 2 Days Budget 30 usd. Details will be shared with interesting bidders

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    FPGA TCPIP implementation using Verilog

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    I have Altera Verilog source code. This is crosspoing from Altera. Add a special feature (essential) to enable any one input (DI) to connect simultaneously to ALLoutputs (DO). Likely part would be EPM570T100I5. You can get source code follow link. [login to view URL]

    €39 (Avg Bid)
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    16 bud

    I have a simple Verilog project. This is very simple. I attached a Logic diagram. Please reference this. Thanks for advance.

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    I want to Verilog programmer. This job i This is very simple. I attached image for logic. You can write code on QuartusII. and then the code must be compiled. Please check image and place bid. Thanks.

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    Compile the redir linux tool ([login to view URL]) for Openwrt 15.05.1 MIPS ar71xx architecture. Not necessary a .ipk package, just a executable.

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    Hi Muhammad Nauman Z., I noticed your profile and would like to offer you my project. We can discuss any details over chat. I have to short questions which i need to answer...noticed your profile and would like to offer you my project. We can discuss any details over chat. I have to short questions which i need to answer, converting c language to MIPS

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    Verilog and Quartus based programming. The project requires a working alarm clock with certain specifications to be met when certain switches are activated.

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    20 bud

    Program counter to be simulated with testbench and implemented on De0-cv fpga. Please see file for exact specificiations and criteria.

    €112 (Avg Bid)
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    19 bud

    Design an Alarm Clock using Verilog and implement it on DE0-CV board using HEX display. Design Specifications for the Alarm Clock • Time should be displayed on the 6-digits of the 7-segment display (HHMMSS). o The left two digits will be the hour, middle two digits will display the minutes and the right two digits will display the seconds. (the period

    €104 (Avg Bid)
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    13 bud

    We are looking for a System Verilog Training for few Engineers in our premises.

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    5 bud

    Design Pipeline processor for RISC based instruction set on Xilinx ISE verilog for Spartan 3E board. Instruction set is given and we need certain kind of output based on designed assembly code. Code should be loaded on Instruction memory and it's already done. we have only 2 days for that but processor is 8bit and instruction is 16bit

    €85 (Avg Bid)
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    ALU The ALU should be coded using these integer operations *, +, -, and /. Register File The register file must be implemented in a separate module. Hex display The hex display must be implemented using a function that converts digits to 7 segment display segments.

    €104 (Avg Bid)
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    19 bud

    Design an Alarm Clock using Verilog and implement it on DE0-CV board using HEX display.

    €157 (Avg Bid)
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    15 bud

    Teach me the concepts of Mips and Intel assembly

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    i need to design 8 bit pipeline line processor in xilinx ISE. It should be in verilog. there is 3 type of instruction set.

    €73 (Avg Bid)
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    5 bud

    Hello, I need some help with Verilog coding. I already have the code but Im having errors and cant compile it. Also, I need hepl with implementing testbench. Teamviewer required to debug the code and I can send you the document to take a look at the project.

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    11 bud

    Hi, I have opencv python programs want to implement them on the ZYNQ SoC. To be in precise want to implement custom object detection(using opencv, tensorflow) on to ZYN...them on the ZYNQ SoC. To be in precise want to implement custom object detection(using opencv, tensorflow) on to ZYNQ board. And also converting the python program to VHDL/Verilog.

    €112 (Avg Bid)
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    7 bud

    Hi Mehmet Fatih A., I noticed your profile and would like to see if you could answer a few questions for me and write a few Assembly (MIPS) programs. The programs are as easy writing a simple five-function calculator, a recursive function to prompt the user for some info and a program that uses dynamic memory allocation to create and manage a linked

    €13 / hr (Avg Bid)
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    - Development Environment Tool : Xilinx Vivado and SDK Latest version Device : Xilinx Zynq7045 HDL : Verilog HDL Required IP Module :HDMI_RX, HDMI_TX Using PG235 [login to view URL] Using PG236 [login to view URL]

    €109 (Avg Bid)
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    3 bud

    Hello, I have the complete knowledge of languages like shell, perl, python, verilog and system verilog.

    €61 (Avg Bid)
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    Hi Iqra Software .., I noticed your profile and would like to offer you my project. We can discuss any details over chat. How many of your team members ar...Iqra Software .., I noticed your profile and would like to offer you my project. We can discuss any details over chat. How many of your team members are experienced with Verilog FPGA programing?

    €36 / hr (Avg Bid)
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    1 bud

    I need image encryption using verilog on FPGA board

    €684 (Avg Bid)
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    13 bud

    I need the services of a Verilog/ Finite State Machine, Logic Control Designer/ Programmer. Good Logic synthesis is required which is basically conversion of a high-level description of design into an optimised gate-level or FSM representation. Regards,

    €25 (Avg Bid)
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    16 bud

    I need verilog code and test bench for implementing Reed Solomon (450,406) encoder and decoder.

    €479 (Avg Bid)
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    11 bud