Hi, I need some help on a Altera FPGA testcase. A 16bit bidirectional parallel data interface on FPGA's pins to write/read to/from a 48bit word FIFO. Written in Quartus 18.1 with Verilog/System Verilog. And a testbench for verification. The FPGA pins used are a 16bit bi-directional data bus, a pin for write enable to bus (active low), a pin for read
I am enclosing description in the files.
Document with full requirements will be shared once discussed with person up for the job. Verilog code in top down design for a 4-bit ALU. A test bench will be needed to test design and needs to be able to program DE0-CV FPGA board to implement the full design.
Verilog/System Verilog module to implement an FSM in the document that will be provided. The 7 segment display on the DE0-CV FPGA board will also be used to show its use. Document will be provided once discussed.
Hello, I found your name in some Verilog source code that another freelancer (Linguang L.) apparently sub-contracted. (Reading data from a PYTHON5000 image sensor). I'm impressed with the work and was wondering if you'd be interested in doing some more, related work.
...games currently work fine, and one of the two modern flash-based cartridges on the market works correctly, but the other one does not. I believe that both of these carts are FPGA-based, and neither one of them is open-source hardware. I'm looking to hire someone to determine the root cause of the incompatibility, and to propose a circuit design modification
...Deo Nano SoC. I have partitioned the RAM and I can write 32bit words to the partitioned area. I have been fighting with Quartus for a while. I can do everything else on this project. I would provide the c-code so you could see how it writes a string of words to the RAM. I also have some VHDL code if you like that is about 98% there. A person skilled in
i need someone teach me how to send and receive data from PCI using c# i have a project need to send and receive data from to FPGA by PCI using c# .net
I require following objectives, methods and methodologies, attached below I require simulation in MATLAB SIMULINK and hardware FPGA
Need verilog modules of VGA_Controller, Oscilloscope, Signal Generator, CDMA Transmitter, CDMA Receiver. The Signal Generator should be generating chips using Walsh Generator.
I want to get VHDL code for Simulation of brain tumor detection on Xilinx ISE design suite and dump on fpga. Fpga available is Zedboard.
project include following 1. data received from uart 2. after samples received, data passed to another module for algorithm execution 3. after execution, data send via uart for display 4. parallel receiving and transmission of data while execution of algorithm 5. design block level diagram 6. test bench code in Verilog 7. project should implement on
I need an assembly MIPS programming language program for demoing my project that did in system verilog language. It should not be more than 250 lines of codes in MIPS and it could be a Maze or Pack Man or another idea depending on the mentor. I will demo this on FPGA that already have these works and files already. here is some description of the task
A verilog module shall be generated, that reboots a 7 series FPGA. It shall be compatible with all 7 series FPGAs, but at least with the following: - XC7A200T-2FBG676C - XC7K160T-2FFG676I - XC7K325T-2FFG676I The module will be tested on existing hardware, which uses master SPI x4 boot mode. The module input should be: - clk - up to 160MHz - reboot
An upload of a song is done from computer to Zybo by using a Wifi Pmod and audio processing operations like low-pass and band-pass filtering using FIR filter with adjustable cut-off frequency and bandwidth will be done on Zybo. The processed audio will be played using audio codec and necessary options will be displayed on a OLED Pmod for selection.
Alarm clock using Verilog and implemented on DE0-CV. Details included in the uploaded file. I need it fast. I know a similar lab has been completed by several of you. This would be minor changes.
I have some projects related to embedded I want them to be done one after other... I am looking for a freelancer having good command over different micro...need a freelancer who do not think too much about money and less focus on work instead i am looking for someone for whom the work Quality must be superior. I will share the project details in chat.
Hi, I have a C++ script which gives me the detections from an SDD detector (running on FPGA+ARM) and it works very good. My script just process the output from the FPGA with OpenCV. Right now, I'm just drawing the bounding boxes around the cars and I'm also counting the detections but I would like to count the cars, not the detections, i.e. a car can
In this project, you will have to design a sequential circuit. The final design will be implemented on an FPGA, therefore, you first have to design an FSM using the hardware description language Verilog.
My Project is object tracking using optical flow on fpga preferably zed board. The application should be able to track a person/ object of interest using optical flow estimation in a HD video. The video is captured through camera n given to the board and the output is obtained through hdmi out of the board which is connected to tv/ computer screen.
The project is to implement object tracking on fpga, preferably Xilinx zed board. The application is to track the object of interest/ person in a HD video. The video captured must be captured from camera and the output given to the hdmi our of the board which can be connected to tv or computer screen
I am fatima zohra , working as intern for a startup company. I need object tracking to be implemented on xilinx zedboard for a HD video. The application should be able to track an object/person of interest from the camera captured video using lucas- kanade optical flow estimation. The output should be obtained through HDMI out which can be connected to computer/ TV screen. Tools like MATLAB , xili...
Mitigate the Harmonics distortion by designing Three phase Hybrid power Filter. I want you to do a simulation in Matlab/Simulink. Design 3 phase Hybrid power filter ( ...passive ) to eliminate the harmonic in both source and load current using SRF theory. And when you are done with simulation then I need to implement & test the controller using FPGA.
FPGA implementation of FOPID controller using VHDL
I need to do Simulation on MATLAB/Simulink. Design 3 phase Hybrid power filter ( shunt active + shunt passive ) to eliminate the harmonic in both source and load current u...power filter ( shunt active + shunt passive ) to eliminate the harmonic in both source and load current using SRF theory. And I need to implement & test the controller using FPGA.