Filtrér

Mine seneste søgninger
Filtrer ved:
Budget
til
til
til
Slags
Evner
Sprog
    Job-status
    3,092 fpga verilog project jobs fundet, i prisklassen EUR
    Verilog project FSM Udløbet left

    Verilog project FSM Verilog project FSM Verilog project FSM

    €9 / hr (Avg Bid)
    €9 / hr Gns Bud
    1 bud

    I need you to develop some software for me. I would like this software to be developed for Windows using Verilog/VHDL.

    €9 - €27
    €9 - €27
    0 bud

    Create verilog code for an Alarm clock with testbenches. Alarm clock will display on 7 segment display. More information available upon request. Simple Project

    €138 (Avg Bid)
    €138 Gns Bud
    1 bud
    PCB Designing 6 dage left

    I need to design a multi layer FPGA PCB in altium.

    €155 (Avg Bid)
    €155 Gns Bud
    5 bud

    This is for the FPGA project.

    €44 / hr (Avg Bid)
    €44 / hr Gns Bud
    1 bud

    Hi, I need some help on a Altera FPGA testcase. A 16bit bidirectional parallel data interface on FPGA's pins to write/read to/from a 48bit word FIFO. Written in Quartus 18.1 with Verilog/System Verilog. And a testbench for verification. The FPGA pins used are a 16bit bi-directional data bus, a pin for write enable to bus (active low), a pin for read

    €177 (Avg Bid)
    €177 Gns Bud
    5 bud

    I am enclosing description in the files.

    €34 / hr (Avg Bid)
    €34 / hr Gns Bud
    4 bud

    Verilog/System Verilog module to implement an FSM in the document that will be provided. The 7 segment display on the DE0-CV FPGA board will also be used to show its use. Document will be provided once discussed.

    €26 (Avg Bid)
    €26 Gns Bud
    6 bud

    Document with full requirements will be shared once discussed with person up for the job. Verilog code in top down design for a 4-bit ALU. A test bench will be needed to test design and needs to be able to program DE0-CV FPGA board to implement the full design.

    €87 (Avg Bid)
    €87 Gns Bud
    11 bud

    Verilog/System Verilog module to implement an FSM in the document that will be provided. The 7 segment display on the DE0-CV FPGA board will also be used to show its use. Document will be provided once discussed.

    €138 (Avg Bid)
    €138 Gns Bud
    2 bud

    Verilog needed to be used Please if you can in between the main block of codes if you can explain the function of that certain code, such as lowering the intern clock to 10Hz, or what not. Thanks

    €19 (Avg Bid)
    €19 Gns Bud
    3 bud

    Hello, I found your name in some Verilog source code that another freelancer (Linguang L.) apparently sub-contracted. (Reading data from a PYTHON5000 image sensor). I'm impressed with the work and was wondering if you'd be interested in doing some more, related work.

    €222 (Avg Bid)
    €222 Gns Bud
    1 bud

    ...games currently work fine, and one of the two modern flash-based cartridges on the market works correctly, but the other one does not. I believe that both of these carts are FPGA-based, and neither one of them is open-source hardware. I'm looking to hire someone to determine the root cause of the incompatibility, and to propose a circuit design modification

    €1103 (Avg Bid)
    €1103 Gns Bud
    6 bud
    Looking for Vivado HLS expert 2 dage left
    VERIFICERET

    Need to know the knowledge of Blockchain algorithm and FPGA programming(VHDL/Verilog), C++ programming. Will discuss more via interview.

    €898 (Avg Bid)
    €898 Gns Bud
    13 bud

    Hi vlsirajagopal, I need help with FPGA configuration, can we discuss the details?

    €220 (Avg Bid)
    €220 Gns Bud
    1 bud

    Hi Rajagopal S., I need help with FPGA configuration, can we discuss the details?

    €220 (Avg Bid)
    €220 Gns Bud
    1 bud

    Hi RKY18, I need to help with FPGA configuration, can we discuss details?

    €220 (Avg Bid)
    €220 Gns Bud
    1 bud

    Hi ducdctoandh, I am interested in FPGA development, could be discuss the details?

    €221 (Avg Bid)
    €221 Gns Bud
    1 bud

    ...Deo Nano SoC. I have partitioned the RAM and I can write 32bit words to the partitioned area. I have been fighting with Quartus for a while. I can do everything else on this project. I would provide the c-code so you could see how it writes a string of words to the RAM. I also have some VHDL code if you like that is about 98% there. A person skilled in

    €204 (Avg Bid)
    €204 Gns Bud
    2 bud
    Verilog code 1 dag left

    Need a verilog code to count spaces in a parking lot using 7 segment led

    €25 (Avg Bid)
    €25 Gns Bud
    14 bud

    i need someone teach me how to send and receive data from PCI using c# i have a project need to send and receive data from to FPGA by PCI using c# .net

    €140 (Avg Bid)
    €140 Gns Bud
    5 bud

    I require following objectives, methods and methodologies, attached below I require simulation in MATLAB SIMULINK and hardware FPGA

    €267 (Avg Bid)
    €267 Gns Bud
    2 bud

    Processor logic design using system verilog

    €49 (Avg Bid)
    €49 Gns Bud
    7 bud

    Need verilog modules of VGA_Controller, Oscilloscope, Signal Generator, CDMA Transmitter, CDMA Receiver. The Signal Generator should be generating chips using Walsh Generator.

    €104 (Avg Bid)
    €104 Gns Bud
    3 bud

    Please find attached file to read more about the project

    €1926 (Avg Bid)
    €1926 Gns Bud
    14 bud

    core for a Xilinx FPGA device 32*32 16bit signed integer core on Xilinx Spartan-6 FPGA device, XC6SLX45-CSG324-3

    €95 (Avg Bid)
    €95 Gns Bud
    8 bud

    I want to get VHDL code for Simulation of brain tumor detection on Xilinx ISE design suite and dump on fpga. Fpga available is Zedboard.

    €20 (Avg Bid)
    €20 Gns Bud
    1 bud

    project include following 1. data received from uart 2. after samples received, data passed to another module for algorithm execution 3. after execution, data send via uart for display 4. parallel receiving and transmission of data while execution of algorithm 5. design block level diagram 6. test bench code in Verilog 7. project should implement on

    €178 (Avg Bid)
    €178 Gns Bud
    5 bud

    Hello I need someone expert in Vivado

    €259 (Avg Bid)
    €259 Gns Bud
    9 bud

    Develop a VHDL or Verilog code using Asynchronous design methodology.

    €71 (Avg Bid)
    €71 Gns Bud
    4 bud

    I need an assembly MIPS programming language program for demoing my project that did in system verilog language. It should not be more than 250 lines of codes in MIPS and it could be a Maze or Pack Man or another idea depending on the mentor. I will demo this on FPGA that already have these works and files already. here is some description of the task

    €279 (Avg Bid)
    €279 Gns Bud
    3 bud
    Tic Tac Toe Game Udløbet left

    develop a code for Tic Tac Toe Game using verilog, for the game square, Implement a Moore state machine for a single square.

    €40 (Avg Bid)
    €40 Gns Bud
    6 bud

    A verilog module shall be generated, that reboots a 7 series FPGA. It shall be compatible with all 7 series FPGAs, but at least with the following: - XC7A200T-2FBG676C - XC7K160T-2FFG676I - XC7K325T-2FFG676I The module will be tested on existing hardware, which uses master SPI x4 boot mode. The module input should be: - clk - up to 160MHz - reboot

    €170 (Avg Bid)
    €170 Gns Bud
    3 bud

    An upload of a song is done from computer to Zybo by using a Wifi Pmod and audio processing operations like low-pass and band-pass filtering using FIR filter with adjustable cut-off frequency and bandwidth will be done on Zybo. The processed audio will be played using audio codec and necessary options will be displayed on a OLED Pmod for selection.

    €222 - €667
    €222 - €667
    0 bud

    Audio processing operations like low-pass and band-pass filtering using FIR filter with adjustable cut-off frequency and bandwidth using wifi PMOD on ZYNQ 7000

    €102 (Avg Bid)
    €102 Gns Bud
    2 bud

    Hi Eslam E., I noticed your profile and would like to offer you my project. We can discuss any details over chat. The project is similar to previous verilog alarm clock codes that you have completed

    €44 (Avg Bid)
    €44 Gns Bud
    1 bud

    Alarm clock using Verilog and implemented on DE0-CV. Details included in the uploaded file. I need it fast. I know a similar lab has been completed by several of you. This would be minor changes.

    €193 (Avg Bid)
    €193 Gns Bud
    5 bud

    I wand to design a project using Verilog to transfer data from USB to a memory with help of USB controller. The usb controller is CYUSB301X/CYUSB201X Memory is EPM2210F256C3N

    €565 (Avg Bid)
    €565 Gns Bud
    5 bud

    I wand to design a project using Verilog to transfer data from USB to a memory with help of USB controller. The usb controller is CYUSB301X/CYUSB201X Memory is EPM2210F256C3N

    €170 (Avg Bid)
    €170 Gns Bud
    4 bud

    I have some projects related to embedded I want them to be done one after other... I am looking for a freelancer having good command over different micro...need a freelancer who do not think too much about money and less focus on work instead i am looking for someone for whom the work Quality must be superior. I will share the project details in chat.

    €20 (Avg Bid)
    €20 Gns Bud
    24 bud
    Project for Eren K. Udløbet left

    Merhaba, ben Levent. FPGA de Sinyal işleme işleri yaptığınızı belirtmişsiniz. Bu tip işlere ihtiyacımız olabilir. Bize şu ana kadar yaptığınız sinyal işleme / dijital uygulamalarından bahseder misiniz. Saygılarımla

    €889 / hr (Avg Bid)
    €889 / hr Gns Bud
    1 bud

    Hi, I have a C++ script which gives me the detections from an SDD detector (running on FPGA+ARM) and it works very good. My script just process the output from the FPGA with OpenCV. Right now, I'm just drawing the bounding boxes around the cars and I'm also counting the detections but I would like to count the cars, not the detections, i.e. a car can

    €248 (Avg Bid)
    €248 Gns Bud
    15 bud

    In this project, you will have to design a sequential circuit. The final design will be implemented on an FPGA, therefore, you first have to design an FSM using the hardware description language Verilog.

    €25 (Avg Bid)
    €25 Gns Bud
    14 bud

    My Project is object tracking using optical flow on fpga preferably zed board. The application should be able to track a person/ object of interest using optical flow estimation in a HD video. The video is captured through camera n given to the board and the output is obtained through hdmi out of the board which is connected to tv/ computer screen.

    €64 (Avg Bid)
    €64 Gns Bud
    1 bud

    The project is to implement object tracking on fpga, preferably Xilinx zed board. The application is to track the object of interest/ person in a HD video. The video captured must be captured from camera and the output given to the hdmi our of the board which can be connected to tv or computer screen

    €90 (Avg Bid)
    €90 Gns Bud
    1 bud

    I am fatima zohra , working as intern for a startup company. I need object tracking to be implemented on xilinx zedboard for a HD video. The application should be able to track an object/person of interest from the camera captured video using lucas- kanade optical flow estimation. The output should be obtained through HDMI out which can be connected to computer/ TV screen. Tools like MATLAB , xili...

    €19 - €161
    €19 - €161
    0 bud

    Mitigate the Harmonics distortion by designing Three phase Hybrid power Filter. I want you to do a simulation in Matlab/Simulink. Design 3 phase Hybrid power filter ( ...passive ) to eliminate the harmonic in both source and load current using SRF theory. And when you are done with simulation then I need to implement & test the controller using FPGA.

    €218 (Avg Bid)
    €218 Gns Bud
    7 bud

    FPGA implementation of FOPID controller using VHDL

    €96 (Avg Bid)
    €96 Gns Bud
    6 bud

    I need to do Simulation on MATLAB/Simulink. Design 3 phase Hybrid power filter ( shunt active + shunt passive ) to eliminate the harmonic in both source and load current u...power filter ( shunt active + shunt passive ) to eliminate the harmonic in both source and load current using SRF theory. And I need to implement & test the controller using FPGA.

    €162 (Avg Bid)
    €162 Gns Bud
    8 bud