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    2,714 fpga freelancer parttime job jobs fundet, i prisklassen EUR

    The parking system has 4 levels, level 1 for admins and disabled, level 2 for staff and disabled, level 3 for visitors and disabled, level 4 for visitors.. we two gates in each level (the gate is a pair of IR sensor) , one gate for entrance and the other for exit.. moreover we have camera and monitor near the entrance gate of level 1 , the camera detects the type of car that entering the parking a...

    €102 (Avg Bid)
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    1 bud

    ...deconding and encoding. this will be run on an MyRIO unit so should either be written for this or easily ported from another DAQ system. Ideally it would utilise the RT Module and FPGA Module and operate with as little overhead as possible. The VI should be able the, in terms of the decoder, output a string or timestamp with the current real time LTC timecode

    €359 (Avg Bid)
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    2 bud

    How does the parking system work? The p...that i am authorized to park only at level 2 and there is only for example 7 vacant lots for staff in level 2. The system is : FPGA ;Nexys 2 spartan 3E, Camera connected to the FPGA, And the monitor connected via VGA to the FPGA, The gates(pairs of IR sensors) in a bread board as illustrated in the abstract.

    €673 (Avg Bid)
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    3 bud

    Need help program FPGA with Artix-7 using Verliog.

    €110 (Avg Bid)
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    5 bud

    We are IT software company. We need someone help me with finding some leads. Sales consultant or Sales partner Who provids leads or take care of sales process. Fulltime or parttime work. We would like to share a work profit. Demand generation companies welcome. Happy bidding.

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    5 bud
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    ARM firmware with LINUX for DE10-Nano board A. Play with the evaluation board 1. Project Owner will provide a P0496 ARM Processor base on Cyclone V SE FPGA computer board (DE10-Nano board). The board will have Ethernet port and SD card. 2. Developer needs to prepare LINUX Kernel to run on embedded computer board with Ethernet TCP/IP to connect with

    €3541 (Avg Bid)
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    21 bud

    Hey, I need help with Verilog / Vivado FPGA project. I'll send you details.

    €154 (Avg Bid)
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    1 bud

    Implement the Zen Protocol in the FPGA and update the Mining App

    €1072 (Avg Bid)
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    3 bud

    Need help program FPGA to communicate with TI7200 through SPI, and generate 300 and 100 Hz sine waves to drive two electric coils,

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    12 bud
    FPGA Designing 2 dage left

    Hello, I need FPGA designing expert. I have complete details of the project. Place your bids, i will share the details with the best bidder. Thank you in advance

    €51 (Avg Bid)
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    10 bud

    We have an in-house trading application which we intend to move to FPGA, using metamako or solarflare fdk

    €70 / hr (Avg Bid)
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    1 bud

    Its a small assignment. If you are an expert and have worked on it before. text me

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    9 bud

    Hi TIV LAbs, I noticed your profile and would like to offer you my project. We can discuss any details over chat. Have you worked on the nexys 4 ddr fpga board?

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    1 bud
    FPGA X13bcd miner and bitstream 1 dag left
    VERIFICERET

    ...looking for someone who can design a FPGA based X13bcd miner to mine X13bcd based coins like BCD. The design should be adaptable for possible changes in the X13bcd algorithm. Use vivado or other software make bitstream for vu9p fpga card with pcie,like xilinx vcu1525. make a miner software for ubuntu or windows. FPGA should be capable of mining with

    €2019 (Avg Bid)
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    10 bud

    The main aim of the project is to design and simulate a Blackjack game model using VHDL and demonstrate it using Alter Cyclone V SoC. The inputs are taken from the play...demonstrate it using Alter Cyclone V SoC. The inputs are taken from the player using the switches and push buttons while the output is displayed on the 7-segment display of the FPGA.

    €327 (Avg Bid)
    Fremhævet
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    1. Design platform: VIVADO 18.2 2. Chip: xcz7020CLG484-1 3. language: Verilog 4. Input is all lvds, fclk is frame clockwise, DCLK is data clock, DDR mode Data receives 16 pairs of ADC data. A pair of LVDS DATA inputs 2 channels of ADC data. FCLK is channel A data when it is high and channel B data when it is low. Output data with 32 channel bit width of 12

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    1. Design platform: VIVADO 18.2 2. Chip: xcz7020CLG484-1 3. language: Verilog 4. Input is all lvds, fclk is frame clockwise, DCLK is data clock, DDR mode Data receives 16 pairs of ADC data. A pair of LVDS DATA inputs 2 channels of ADC data. FCLK is channel A data when it is high and channel B data when it is low. Output data with 32 channel bit width of 12

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    6 bud

    Need to Build the FPGA to HPS DMA code in Arria 10 Intel-Altera FPGA

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    2 bud

    fpga pattern generator connected to a pc starting from an evaluation board and an HDL from TI.

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    Project target is to have a FPGA to communicate with two I2S codecs and to provide a SPI slave connection conveying the I2S data to and from a local MCU. Testing scripts and test timings for the Altera Quartus environment are required. For the proper testing of the project deliverables, test scripts and test timings need to be created and relevant

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    I need to perform video compression using FPGA My final aim is to get a .bit or to .bin file so that I can burn the image to my fpga and simply voila.. Kindly visit this link in order to get an insight to the board that I will be using… [log ind for at se URL] I want video to

    €139 (Avg Bid)
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    I have my FPGA Xilinx Artix 7 XC7A50T development platform for my personal project. It has DDR3, Hi-speed ADC, Hi-speed DAC, UART, SPI(x2), IIC, and an Ethernet MAC. I need a complete design with microBlaze. I can provide a small example xpr prj but not yet finished. I need someone to configure and link the ip together and have it finally synthesis

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    9 bud

    Need a vhdl expert for Vhdl Code modification. Clock divider and counter design. Code needs to be run on an fpga. Thanks

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    Hi I need codeigniter developer for parttime work. Task will be allocated as per task of project and once task is completed, payment will made to developer on same day. I PREFER ONLY FREELANCER. NOT ANY COMPANY.

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    If, you wish to travel around the world. If, you would love to live differently, and take steps further. The Travel E...who like flexible working hours 5. People who only have a fixed income and are willing to work harder Full-time / Part-time are always Welcomed if you are interested. #Parttime #Fulltime #TravelExpericer Contact Me To Know More.

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    I'm trying to port PYNQ over to a diligent board that is not directly supported. I'm hoping somebody has already done this that would be willing to share their SD card files with me to save me the trouble. I'm looking for PYNQ version 2.2 or 2.3. Please and thankyou.

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    Magento fulltime/parttime developer in Ahmedabad per Hour basis / Fixed rate Minimum 2-4 yrs of experience Magento 1.9 & 2.0 expert Theme modification module creation Magento core files and framework knowledgeable Magento hosting knowledge Magento ssh command line expert GitHub knowledge knowledge of bigcommerce and WordPress would be an advantage

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    D Class Amp Udløbet left

    Design of a D class amp. Digital Input to DAC from FPGA . VHDL files for Digital Input will be provides. Amplification part of the circuit to have a Mosfet setup. DAC and Mosfets have been selected. Full circuit simulation to be done in Tina software.

    €232 (Avg Bid)
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    Hello, I have developed the full game in verilog, but I need help with a game over screen to pop up with the player loses all of his lives or a win screen with the player has beaten the game. I will provide you with all the code, mifs, rams, and I just need help to implement the win and game over screens.

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    ProjectDone Udløbet left

    The project is over VHDL using Vivado software, and it contains five smaller parts. have a fun with FPGA and hardware language.

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    12 bud
    abiramiamanm Udløbet left

    vlsi coding using QUARTUS II software FPGA

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    We are looking for an implementation of a FPGA SATA-to-SATA bridge. Design should be made in VHDL and be compatible to Xilinx Aritx-7 Series. The FPGA should receive SATA as a device (SATA device controller) and forward these information after processing to one or two SATA devices as SATA host (SATA host Controller).

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    ...de la arquitectura del juego de instrucciones del RISC-V. El microcontrolador debe ser descrito en SystemVerilog de modo que sea sintetizable y pueda ser implementado en una FPGA Cyclone IV de Altera. Su validación experimental se realizará en el laboratorio mediante una aplicación sencilla propuesta por cada grupo que haga uso de los recursos hardware

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    Digital To Analoge Udløbet left

    ...Piazo Printhead. I am looking for a engineer with experience in sending Digital Data to a DAC setup and amplified via Mosfets. Digital Data will be implemented on a Xilinx FPGA. Trapezoidal waveform needs to be written in VHDL so that circuit and Code simulation can be done in Tina software. An explanation of the VHDL code to be supplied so that

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    Develope script in XILINX ISE FPGA using nexys 4 ddr card Language VHDL For calculator

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    ...de la arquitectura del juego de instrucciones del RISC-V. El microcontrolador debe ser descrito en SystemVerilog de modo que sea sintetizable y pueda ser implementado en una FPGA Cyclone IV de Altera. Su validación experimental se realizará en el laboratorio mediante una aplicación sencilla propuesta por cada grupo que haga uso de los recursos hardware

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    4 bud
    Nodejs and Angular Udløbet left

    We are looking to hire a fulltime to a parttime nodejs and angular developer to finish some projects that we would like to get done on our website. We are looking for a developer to add to our team. We are looking for the developer must be able to give us there best hourly price. Preferred is a developers with 5+ years of experience with nodejs and

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    Need to update VHDL and C-Code for change the communication from PCI-e to USB. The target is a Xilinx FPGA

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    We are Hiring Good Programmer in FPGA, GPU, CUDA, MATLAB for our Company. (Removed by Freelancer.com Admin)

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    The project is described in the uploaded file, however one can alter the project as long as keeping the equipments and the goal of the project intact

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    Graphics Desinger Udløbet left

    We are a product based statup company.. we need one graphics designer parttime of full time.. Freshesrs are welcome with thir portfolio they have..

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    ...be 3 different block RAMs, or 2 block RAMs and “LUTRAM” created by using a logic block as RAM). Your CAD tool should attempt to find a solution that minimizes the area of the FPGA needed to fit each benchmark circuit....

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    ...be 3 different block RAMs, or 2 block RAMs and “LUTRAM” created by using a logic block as RAM). Your CAD tool should attempt to find a solution that minimizes the area of the FPGA needed to fit each benchmark circuit....

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    ...player's movement should not be pixel by pixel but rather, it should keep sliding until it hits the wall(boundary). The movement control should be done through the keys on the FPGA. The maze should have a fully functional non-flickering background, which should be easily be replaced. It should also have a start and game over screen. The work should have

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    I need someone to write verilog code and also test .do files for a simplified board game. The program should output to vga. the game is quite simple ;2 players ro...imported from a library etc. The work should have lots of comments ,documentation and test (.do) files so that it can be easily understood by a beginner. it should work with a FPGA board.

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    I need an FPGA selected and hardware design created for decoding of an MPEG-Transport Stream parallel interface from a DVB-T demodulator. The FPGA needs to decode the transport stream and extract the video data as well as any other data contained in the Transport stream, the FPGA must then extract a selected individual pixel, and its colours are extracted

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    ...you can modify that but I need the code running on FPGA board after I download it to it. Description: You have to create the VHDL model for the 4-bit multiplier. You must also synthesize the VHDL model, download to FPGA and test your multiplier on the FPGA board. Use a push button on the DE10-Lite FPGA to provide the clk input to the multiplier. The

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    Custom FPGA Project Udløbet left

    This is a multi-part project for the Lattice MACHXO2-4000 LOGIC IC.

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    Looking for a developer to interface high speed TI DAC with virtex 7 FPGA. I am having DAC34H84 DAC and VC707 kit- and want to interface the same DAC with VC707 Hardware that i have is DAC34H84 and VC707

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    10 bud