We are working on an FPGA based doppler flowmeter with a custom PCB. At the moment, we are in the process of modeling algorithms using raw data recording in Matlab. This freelancer will be tasked with coordinating with the DSP engineer to design and implement changes from the Matlab models into our custom PCB, which Cyclone IV based. There is an existing
Project requirements will be provided after talking.
I have a digital input measurement signal, 0 ~ 1.1V level. Each pulse is an event, that has a level HIGH width from 5ns to 10ns, and the minimum time between every 2 pulses' rising edges is 20ns. I need a system to histogram the time between all adjacent pulses' rising edges, that each bin of the histogram is 1ns wide. For example, starting from t=0, if the input signal has rising edge...
Hi, I need some help on a Altera FPGA testcase. A 16bit bidirectional parallel data interface on FPGA's pins to write/read to/from a 48bit word FIFO. Written in Quartus 18.1 with Verilog/System Verilog. And a testbench for verification. The FPGA pins used are a 16bit bi-directional data bus, a pin for write enable to bus (active low), a pin for read
Document with full requirements will be shared once discussed with person up for the job. Verilog code in top down design for a 4-bit...once discussed with person up for the job. Verilog code in top down design for a 4-bit ALU. A test bench will be needed to test design and needs to be able to program DE0-CV FPGA board to implement the full design.
Verilog/System Verilog module to implement an FSM in the document that will be provided. The 7 segment display on the DE0-CV FPGA board will also be used to show its use. Document will be provided once discussed.
...games currently work fine, and one of the two modern flash-based cartridges on the market works correctly, but the other one does not. I believe that both of these carts are FPGA-based, and neither one of them is open-source hardware. I'm looking to hire someone to determine the root cause of the incompatibility, and to propose a circuit design modification
I'd like to invite you to take a look at the job I've posted. Please submit a proposal if you're available and interested. It is about a few hour job. I am using the Deo Nano SoC. I have partitioned the RAM and I can write 32bit words to the partitioned area. I have been fighting with Quartus for a while. I can do everything else on this project. I would provide the c-code so you c...
i need someone teach me how to send and receive data from PCI using c# i have a project need to send and receive data from to FPGA by PCI using c# .net
I require following objectives, methods and methodologies, attached below I require simulation in MATLAB SIMULINK and hardware FPGA
I want to get VHDL code for Simulation of brain tumor detection on Xilinx ISE design suite and dump on fpga. Fpga available is Zedboard.
project include following 1. data received from uart 2. after samples received, data passed to another module for algorithm execution 3. after execution, data send via uart for display 4. parallel receiving and transmission of data while execution of algorithm 5. design block level diagram 6. test bench code in Verilog 7. project should implement on zedboard [log ind for at se URL] code explanatio...
...system verilog language. It should not be more than 250 lines of codes in MIPS and it could be a Maze or Pack Man or another idea depending on the mentor. I will demo this on FPGA that already have these works and files already. here is some description of the task. Every demo must use the VGA monitor as an output device. By default, every demo should
A verilog module shall be generated, that reboots a 7 series FPGA. It shall be compatible with all 7 series FPGAs, but at least with the following: - XC7A200T-2FBG676C - XC7K160T-2FFG676I - XC7K325T-2FFG676I The module will be tested on existing hardware, which uses master SPI x4 boot mode. The module input should be: - clk - up to 160MHz - reboot
An upload of a song is done from computer to Zybo by using a Wifi Pmod and audio processing operations like low-pass and band-pass filtering using FIR filter with adjustable cut-off frequency and bandwidth will be done on Zybo. The processed audio will be played using audio codec and necessary options will be displayed on a OLED Pmod for selection.
I have some projects related to embedded I want them to be done one after other... I am looking for a freelancer having good command over different micro controllers and also know how to couple different kind of sensors with different controllerts I need a freelancer who do not think too much about money and less focus on work instead i am looking for someone for whom the work Quality must be supe...
Hi, I have a C++ script which gives me the detections from an SDD detector (running on FPGA+ARM) and it works very good. My script just process the output from the FPGA with OpenCV. Right now, I'm just drawing the bounding boxes around the cars and I'm also counting the detections but I would like to count the cars, not the detections, i.e. a car can
In this project, you will have to design a sequential circuit. The final design will be implemented on an FPGA, therefore, you first have to design an FSM using the hardware description language Verilog.
My Project is object tracking using optical flow on fpga preferably zed board. The application should be able to track a person/ object of interest using optical flow estimation in a HD video. The video is captured through camera n given to the board and the output is obtained through hdmi out of the board which is connected to tv/ computer screen.
The project is to implement object tracking on fpga, preferably Xilinx zed board. The application is to track the object of interest/ person in a HD video. The video captured must be captured from camera and the output given to the hdmi our of the board which can be connected to tv or computer screen
I am fatima zohra , working as intern for a startup company. I need object tracking to be implemented on xilinx zedboard for a HD video. The application should be able to track an object/person of interest from the camera captured video using lucas- kanade optical flow estimation. The output should be obtained through HDMI out which can be connected to computer/ TV screen. Tools like MATLAB , xili...
Mitigate the Harmonics distortion by designing Three phase Hybrid power Filter. I want you to do a simulation in Matlab/Simulink. Design 3 phase Hybrid power filter ( ...passive ) to eliminate the harmonic in both source and load current using SRF theory. And when you are done with simulation then I need to implement & test the controller using FPGA.
FPGA implementation of FOPID controller using VHDL
I need to do Simulation on MATLAB/Simulink. Design 3 phase Hybrid power filter ( shunt active + shunt passive ) to eliminate the harmonic in both source and load current u...power filter ( shunt active + shunt passive ) to eliminate the harmonic in both source and load current using SRF theory. And I need to implement & test the controller using FPGA.
Hi, I am interested in building a very simple demo for a software application I would like to build. The UI is similar to QT Node Editor. I want to make a Python / RTL to FPGA application. Similar to DSP builder for Intel, but different. QT Node editor look and feel. What is your email?
The system will get command through SPI channel to generate custom frequencies (between 0.05hz to 1khz) in 10000 samples for a cycle and save it to a look-up table And in the second command will send the values of the sine-wave to Digital to Analog device
Project target is to have a FPGA to communicate with two I2S codecs and to provide a SPI slave connection conveying the I2S data to and from a local MCU. Testing scripts and test timings for the Altera Quartus environment are required. For the proper testing of the project deliverables, test scripts and test timings need to be created and relevant documentation
I want an MP3 player built on FPGA board based on VHDL language. I want a seasoned hands on FPGAs who can build me this by Apr 2nd, 2019. The FPGA board I have is Xilinx Spartan-6 LX45 (Atlys circuit board) specifically on which it will have to be built and synthesized. I have uploaded an image of the board and feel free to ask me for any information
Schematics checking -Zynq7020 fpga -1GB RAM on PL (For post post process) -1GB RAM on PS -Network PHY RTL8211E-VL -USB PHY USB3320 -Run and Boot OS Via QSPI MT25QL256ABA -SD Card -Check on the power regulator boot up sequence. Suggesting - where and which bank/emio to connect the SFP fiber optic. Prefer no using additional dedicated PHY. SGMII will
I need a basic board game, where two players take turns rolling a dice and going around a board similar to monopoly. Once they comple...around the board once, the game ends. The player with the most coin wins. If they land on certain spaces they loose coins and some they gain coins. It has to work on Cyclone V FPGA board using Assembly and C on armv7.
The brightness measurement with help of PMODALS sensor ([log ind for at se URL] ) should be realized. For this purpose, the Basys 3 FPGA board should be used. Furthermore, an 8051 microcontroller IP core([log ind for at se URL]) is to be used, which takes over the control. The
FPGA IMPLEMENTATION of VHDL coding of CONTROL UNIT SYSTEM
We want a DDR3 controller for a 7 series FPGA with the following specification: - DDR3 Speed: 533MHz (DDR3-1066) - DDR3 component: MT41K1G8SN-125:A - FPGA: XC7K160T-2FFG676I The controller shall have the following interfaces to the top level: - AXI slave for incoming write data - 32bits width - AXI master for outgoing read data - 32bits width - write
Hi, I have a C++ script which takes the frames from a SDD detector (running on FPGA+ARM) and it works very good. My script just process the output from the FPGA with OpenCV. I have added some counters to count the numbers of elements detected (vehicles and pedestrians). It counts a lot of elements because it counts in every detection. I would like