Cpld project designJobs

...Cisco ASR 1004 rp2 Software and Romon,cpld,fpga Update Description: I am looking for a skilled professional who can assist me in updating the software and components of my Cisco ASR 1004 rp2 device. The main focus of this project is to update the software, Romon, cpld, and fpga. Current Software Version: I am not sure, please check for me. Specific Features/Fixes: I am not sure, please recommend. I am open to suggestions on the latest version and any specific features or fixes that would enhance the performance and functionality of my device. Backup: Yes, I have a backup of my current configuration and data. Ideal Skills and Experience: - Strong knowledge and experience with Cisco ASR 1004 rp2 devices - Expertise in updating software, Romon, cpld, and ...

We are looking to replace a Graphics LCD display with 320x200 pixel resolution using a SED1330/1335 Controller with a modern TFT or OLED based solution with 400x300 pixel resolution . The scope of the project will be to suggest a low power ,MCU suitable for this task or a FPGA/CPLD based solution , develop and debug the code to convert the data from the SED1330 commands to serial commands the new display can process and scale the data to fit the higher screen resolution . All hardware design will be performed by us

Design Problem specification: To design and implement an autonomous Self-Navigating robot. The robot should be trained and programmed to reroute its path when colliding with the objects in its path. You will be required to partition the problem into suitable hardware and software units, verify the components, integrate these components into a complete system, verify and test. The documentation should show justification for any design decisions that you make as well as development logs for both hardware and software. Evidence of approaches used for the co-design, co-implementation, co-testing, co-integration and system integration has to be provided. This assignment will provide experience of the problems and decisions in developing co-design proj...

Need help with Lattice CPLD Verilog design - - simple power sequencing, GPIO registers control, I2C, RS232

I have a board that I need to have another build. This board has about 5x7cm and has 2 layers. It also has 13 components, among them an 39sf040 flash and a ATF1502AS CPLD. The job consists in producing the schematics needed so I can be able to order the PCB prints and assemble the components. If possible I would also like the reading of the CPLD into a binary file so I can use to write other CPLDs. I can provide high resolution scans or, eventually, send the the board for a closer look.

Need to create a 8052 softcore on a CPLD which will communicate with some Logic ICs, external SRAM Memory. No restrictions on Timing as such.

Making a JRPG style game for the 1980s original Nintendo. As it stands most cartridges only support 512KB of data. Since I'm wanting to have the game not have any repeat monsters that are colour swapped, this takes up a fair amount of data. And thus ra...like to keep the cost per chip around the $5 or less. It'll also give me time to think if anything else might be needed on the board. IE: 8KB Work-RAM, that uses a battery to stay active that's used for saving the game I actually already designed a 2MB cart. ? For the most part it will meet my needs. The reason I want to use CPLD Like the XC9572XL and a larger flash memory is to get the ability to use wav files for music and better sound then what's available. The design that I showed before did this, bu...

A simple CPLD DEVICE performs actuator functionality in an UAVs Looking for engineer who can verify the block level logic by verifying writing Test case Test bench Test procedure Simulation results

This targets a CPLD to implement all circuits using a Schematic Entry approach i.e. using Component Macros in the ISE environment. The major required components are specified in each part. Minor components such as gates are assumed to be self-evident. Using:- Xilinx ISE software (Schematic entry, synthesis and simulation) Adept Software (Programming utility for CPLD)

...same samplerate, selectable 48/96/192KHz, connected to a CPLD and the CPLD to provide a TDM protocol for connection to a MCU. Codecs will have 48/96/192KHz, stereo, 32bits sample depth and will work at I2S protocol. Codecs will perform both capture and playback concurrently. The TDM protocol should have 4 slots for channels. Some points that need to be taken into consideration in order to better understand the requirements: 1. the freelancer must have good kowledge of audio TDM and I2S protocols. 2. The freelancer should decide what CPLD is most appropriate and cost beneficial to the task, CPLD has to be a member of Intel/Altera MAX V CPLD. 3. The freelancer will provide appropriate testbech to verify the proper behaviour of the design with w...

I have some code for a xilinx CPLD that needs to converted to verilog or vhdl here is a snippet of the code...... I know that there is a xilinx utilty to do that, but I am too busy "rf control "this sets the pins "the power enable = !(!pld_wr & (addr == CONT)); = 0; = 0; rf_cont := [d4..d0];

A Freelancer with skills in digital logic design is needed to write a small program for a CPLD device using WinCUPL. Atmel/Microchip devices would be used. The CPLD will manage clocking a fixed byte stream into a FIFO ic. The byte stream will not pass through the CPLD device. The program should be simulated and verified. Please see attachments and feel free to offer suggestions.

The goal of the project is to translate an LCD bus with propriety signaling to drive a standard off the shelf LCD using RGB interface. In addition, the image will require interpolation while keeping the original aspect ratio. Source device will be provided + timing chart of source. Output LCD + LCD controller datasheet + init code will be provided. Development board will NOT be provided (you should have your own). VHDL is preferred but not obligatory, Verilog can also be used. Altera family devices should be used. Project should be oriented towards low power and low cost since day 1. Information about further requirements (some software features) will be provided later. Please read this before quoting. Please do not quote if you can not complete this project. Pl...

Design and construct a Digital Frequency Meter System capable of measuring the frequency if input sinusoidal signals for the range 0-500kHz, with a resolution of 0.1Hz, and voltage levels 0-3.1Vpk-pk. The frequency of the input sinusoidal signal must be displayed on the Diligent Coolrunner-II CPLD board. I have included the files required to construct the FSM. The files just need to be modified and integrated for the FSM to function.

Create a custom SPI master controller with single, dual, and QUAD operation modes in VHDL for a MAX V CPLD.

1. Identify a good value and properly sized CPLD/FPGA and toolset (toolset needs to be relatively easy to configure) to accommodate the required functionality. 2. Develop the CPLD/FPGA code. The device needs to take as inputs a set of states (from a microcontroller so either as an I2C command or as a 3 digital input code, along with 3 digital inputs - alarms). The device then needs to set 11 outputs based on a 4 input truth table. 3. A basic schematic for implementing the hardware, preferably in Altium.

I have a short project to do for an Altera 5M160Z CPLD (160 LE). This board has a 16-bit bus from a MCU and 8 control lines and output to a 10-pin port. What I need is a VHDL project (Quartus) that will implement a custom full duplex parallel to serial design. Development using simulation is fine.

Hi there, I am looking for someone to design 16x16 crosspoint matrix using CPLD. I attached 3 pdfs and please look at those carefully. I need to finish my project in 1 day. This is very easy project.

...2007, and many of the specific parts no longer are in production (CPLD, memory, even some resistors and diodes). We require an RF engineer to go through the BOM and update the list with modern components easily sourced from DigiKey, Newark, Mouser, etc, without a significant re-design of the boards themselves. Ideally, the successful candidate would also be able to re-write the FPGA firmware to accommodate a faster ADC chip. We are currently using an 80 MSPS 14 bit ADC (AD9245BCPZ-80), which is the fastest in that specific form factor. Ideally, we would like to go as high as 180 MSPS whilst keeping the board the same size. This would require some re-work of the board and a re-writing of the FPGA code. We do have a design for a modern Rx board, but have no firm...

1) Implement high-speed 8-bit bus for MCU (ATSAM3U) to connect to Altera CPLD (5M160ZM68C5N) 2) Implement SPI Mode-0 SPI Slave in CPLD logic 3) Implement Dual SPI Slave mode in CPLD logic 4) Implement QUAD SPI Slave mode in CPLD logic 5) Implement general purpose I/O (8-bit) Port B in CPLD logic 6) Implement JTAG Host shift logic in CPLD logic

CPLD design (preferably for Xilinx XC2C64A) to implement a SPI to custom IF (serial to 8-bit parallel with differential clock and read strobe).

FPGA design ( actually MAX V CPLD). Requires good knowledge of Altera Quartus II manual layout, routing, schematic capture. Altera serial ( RS232 or SPI) and Gray counters IP library blocks will be used. Will work interactively with the designer.

Project goal: Help design and implement a NAND Flash memory interface for a CPLD that will interface between a high-performance MCU and a NAND Flash device. Details: The CPLD will connect to the MCU using SPI (SO,SI,CLK,CS) and a DMA enabled memory I/O port (16-bit) and the CPLD will interface with the NAND memory using standard control, address and data lines (CE#,WE#,RE#,AKE,CLE,DQS and DQ0-DQ15). The SPI will be used to setup the controller's configuration (timings, sync/async, initial 40-bit address, number of address cycles, X8 or X16 mode, etc.) and also issue the operation (read/write DQ). The CPLD will also need to be able to be configured to interface with either 1.8V or 3V NAND memory. A single pin supply (for the CPLD BANK...

Implementation of Image processing algorithms on FPGA/CPLD hardware using VHDL, and Verilog, MATLAB

Looking for a motivated individual to join the team and get our project off the ground. We are an early-stage start-up that needs help with building and developing a prototype. The poject revolves around IoT and requires this engineer to lead the charge in building the H/W component of our system. The prototype will be an IoT. We will pay for the different modules required to build this system, but require the engineer to make an accurate parts list (milestone). Examples of modules used for prototype development: - Networking and Communication: Ethernet, Wirless, Bluetooth, RF, NFC - Wearable: Accerlerometers, Gyroscopes, Altimeters, Timer, and Counter - IVR: Voice Recognition modules, Speakers, and Microphones - Power Supply A brief Job Description: - Working knowl...

Hi mastor3...your profile and would like to offer you my project. We can discuss any details over chat. The project I am wishing to do is implement a basic circuit in CPLD, the circuitry has a 27C010 flash ROM IC and some basic 7400 series logic ICs. I would like the CPLD to have a ICSP port for updating and also another header for changing a ROM in the emulated 27C010. These can share the same port if appropriate. I can provide a schematic showing this circuitry. Please let me know if you have interest in this project and we can discuss the details and a quote. I will set the price low when i send this message, but we can adjust the pricing through milestones once you understand the aspects of the project. I will implement this CPLD ...

I am working on a project to control some device with CPLD with VHDL in xilinx. i need some help with some error, proofread, and add one small feature

We need to interface an ADC with SPI output and a MCU. We have a draft design of a CPLD using Quartus II Schematics editor for an inexpensive CPLD such as Altera's Max3000A series. We can provide a full description of the inputs and outputs required and the full functionality. As we are overloaded, we need a freelance engineer to finish up the CPLD architecture using Quartus II and run a few simulations to validate it. To finish the project the design should be ready to program the CPLD using the Blue Blaster programmer. We will do all the hardware testing. This is a realatively simple CPLD project for an experienced engineer.

...candidates that passed HR interview. Required Qualifications: - Bachelor or Master’s degree in Electrical Engineering or equivalent - 10+ years of experience in electronics production design - Ability to write and debug FPGA and CPLD code - Experience with microprocessor, FPGAs and CPLDs, high-speed transceivers, DDR and flash memories, block diagrams, parts lists and design review packages for complex electronics - Experience with interfaces and bus standards such as PCIe, USB, I2C and etc. - Demonstrated capability in leading a group of design engineers in the design and development of an HW project from concept through production - Wide knowledge of PCB layout, Signals Integrity and simulation - Proven experience with han...

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We have a program in ABEL language for Xilinx XC9572. We want someone to convert the file to VHDL or .JED so that we can burn it on XC9572 Devices

Hi Ars4r3Lancing, I noticed your profile and would like to offer you my project. We can discuss any details over chat. I have some simple XILINX cpld file written in .abl I want to be converted to verilog, to run on XC2C64A cpld. These are quite basic, and I have a number of them. Are u interested in this task ?

Hi RiverK330, I noticed your profile and would like to offer you my project. We can discuss any details over chat. I have a number of XILINX CLPD .abl files I want rewritten in verilog. Are you interested ? They are quite simple...64 macrocell cpld devices. Are you familiar w .abl ?

Hi rohi1710rohi1710, I noticed your profile and would like to offer you my project. We can discuss any details over can discuss any details over chat. I need to help in writing Verilog code for an FPGA or CPLD which will take an SPI type of data and to interface to 2 16 Bits D/A converters. SPI data basically converts to analog voltage. Can you Xilinx, Altera. the D/A's will need to be specified by the coder after review of current design. The D/A must output +/- 10V signals. The deliverables will be Verilog code only, and the manufacturer part number for the FPGA and DAC devices. There is no need to design any of the electronics. The reference schematic will be used for you to see how these components will work together.

Hi rohi1710rohi1710, I noticed your profile and would like to offer you my project. We can discuss any details over chat. I need to help in writing Verilog code for an FPGA or CPLD which will take an SPI type of data and to interface to 2 16 Bits D/A converters. SPI data basically converts to analog voltage. Can you Xilinx, Altera. the D/A's will need to be specified by the coder after review of current design. The D/A must output +/- 10V signals. The deliverables will be Verilog code only, and the manufacturer part number for the FPGA and DAC devices. There is no need to design any of the electronics. The reference schematic will be used for you to see how these components will work together.

Hi SANGITAR, I noticed your profile and would like to offer you my project. We can discuss any details over chat.I need to help in writing Verilog code for an FPGA or CPLD which will take an SPI type of data and to interface to 2 16 Bits D/A converters. SPI data basically converts to analog voltage. Can you Xilinx, Altera. the D/A's will need to be specified by the coder after review of current design. The D/A must output +/- 10V signals.

Hi oharwot, I noticed your profile and would like to offer you my project. We can discuss any details over chat. I need a coder who can write in Verilog code for an FPGA or CPLD which will take an SPI type of data and to interface to 2 16 Bits D/A converters. SPI data basically converts to analog voltage. You can use Xilinx or Altera. the D/A's will need to be specified by the coder after review of current design. The D/A's must output +/- 10V signals.

I am designing and building a drive circuit for a large array of LEDs. The arrangement of the LEDs, in terms of amount of strings and amount per string, is adjustable depending on the drive circuit topology. However, after reviewing the DC-DC converter IC options available, I am considering generating my own converter, using a CPLD (or other comparable programmable device) with an external FET. I am looking for assistance in setting up the memory and internal programming. I have experience in this area, but not so much that I won't pay for assistance

Hello, I need a CPLD chip designed, can you be of assistance?

Design electrical for LPC1768, STM32, DSP, CPLD, FPGA or the other digital experienced of the sensor circuit and control circuits.

1. System architecture (design a multi header linescan CCD system that connects to a PC via ethernet. System would be based on microntroller and CPLD/FPGA) 2. Schematic designing 3. PCB layout designing in Altium 4. Firmware development 5. SDK/DLL in C# for interface with windows based software 6. test utility to view data from the controllers . To be made in C#

Job Description - Embedded Software/Firmware Engineer w/ 7+ yrs BIOS, board bring up, C programming, embedded bootloader, must relocate ...Description - Embedded Software/Firmware Engineer w/ 7+ yrs BIOS, board bring up, C programming, embedded bootloader, must relocate to Utah - Civil Engineers, 3-6 yrs exp in land development - Civil Engineers w/ PE license, 7-13 yrs exp in land development - Transportation Engineer w/ PE license, 10-15 yrs exp in highway/roadway design projects - Electrical Engineer w/ 7+ yrs FPGA/CPLD digital design exp, must relocate to Utah - Electrical Engineer w/ 7+ yrs Hardware Design Verification & Test, assist with hardware/PCB debug/development, must relocate to Utah ****PLEASE READ***** - Candidates MUST be US citizen...

VHDL coding for CPLD device to test signals of TTL,differential,SPI etc.

...assist by reviewing my design and help resolve issues I’m experiencing. I have a project that is experiencing what I believe to be timing issues. The project is an 8Meg RAM Card for an Apple IIgs, and there are 2 versions of this computer (ROM1 and ROM3). Both have slightly different timings, but are basically compatible. I currently have a proto PCB I am working with. The project is laid out using Schematic Entry since I have no VHDL knowledge. I have been adding gates and setting net attributes in order to adjust timings in an attempt to achieve a design that works on both versions of the Apple IIgs. I believe if the address and /CAS and /RAS signals could all be latched or clocked, then the design would be stable, however I&...

...Composite and Analog RGB output is slightly different than what the industry standards were. This needs to be accounted for in the Adapter’s design. Differences are documented online, and I can provide additional links and clarification if needed. This project MUST be able to reproduce video artifacts, also called “color fringing”, when displaying color on a modern display. In short – this means when one color pixel was displayed adjacent to another color pixel, a third color would be produced. Many programs and games used this feature to expand the limited color pallets available on the old computers. Project Scope: You will provide project source code and electronic schematics. All work will preferably be housed on my Go...

To write the VHDL code for the behavioral specification of the SPI Slave and Master Interface and to implement the write and read operation on SRAM using CPLD board.

We are in the process of reworking an old design that used a Lattice ispLSI1016 CPLD. Unfortunately we no longer have any source files. All we have is a JEDEC file that we currently use to program CPLDs. We contacted Lattice to ask about moving from the older design in to a newer CPLD and they said without any source files it would be impossible. So we are researching if anyone has ideas for a solution to reverse engineer the CPLD in to either a schematic or new source files/code. Please contact us to get the JEDEC file. Any and all input or ideas are welcome, and any viable leads or assistance will be rewarded. Please ask if there are any questions. Thanks!

I have a simple multiplexer circuit that uses off the shelf 74LS logic chips. Years ago this circuit was converted from off the shelf parts to Verilog for a CPLD to save much needed space. The platform selected at the time was Atmel's Chip Designer using the ATF150x CPLD. The Atmel CPLD's are a little large compared to todays offerings. Atmel's software also doesn't run well on any newer PC. The decision was made to move to a new CPLD platform, that being Altera's Quartus SP13. The CPLD we've selected to use is the 3000A with a pin to pin delay of 10ns. Due to the new CPLD and new software, our simple multiplexer circuit (written in Verilog) still works but has timing issues. In order to get it to run almost perfect, I ...

Create and Implement a simple Circuit design using Xilinx's VHDP and CPLD -Important Source code is a must A simple sample image of the Circuit is provided below

create a simple project using VHDL and CPLD